-
公开(公告)号：US20080098190A1
公开(公告)日：2008-04-24
申请号：US11963913
申请日：2007-12-24
申请人： Yoshinori Takase , Keiichi Yoshida , Takashi Horii , Atsushi Nozoe , Takayuki Tamura , Tomoyuki Fujisawa , Ken Matsubara
发明人： Yoshinori Takase , Keiichi Yoshida , Takashi Horii , Atsushi Nozoe , Takayuki Tamura , Tomoyuki Fujisawa , Ken Matsubara
IPC分类号： G06F12/00
CPC分类号： G06F12/0246 , G06F12/0893 , G06F2212/2022 , G06F2212/7203 , G11C16/06 , G11C16/10 , G11C16/26 , G11C2216/22
摘要： A non-volatile storage device (1) has non-volatile memory units (FARY0 to FARY3), buffer units (BMRY0 to BMRY3) and a control unit (CNT), and the control unit can control a first access processing between an outside and the buffer unit and a second access processing between the non-volatile memory unit and the buffer unit upon receipt of directives from the outside separately from each other. The control unit can independently carry out an access control over the non-volatile memory unit and the buffer unit in accordance with the directives sent from the outside, respectively. Therefore, it is possible to set up next write data to the buffer unit simultaneously with the erase operation of the non-volatile memory unit or to output once read storage information to the buffer unit at a high speed as in a cache memory operation in accordance with the directive sent from the outside. Consequently, it is possible to reduce the overhead of a data transfer for reading/writing data from/to the non-volatile storage device.
摘要翻译： 非易失性存储设备（1）具有非易失性存储单元（FARY 0至FARY 3），缓冲单元（BMRY 0至BMRY 3）和控制单元（CNT）），并且控制单元可以控制第一访问处理 在外部和缓冲单元之间以及从外部分别接收到伪指令之后的非易失性存储单元和缓冲单元之间的第二访问处理。 控制单元可以分别根据从外部发送的指令独立地对非易失性存储器单元和缓冲单元执行访问控制。 因此，可以与非易失性存储器单元的擦除操作同时地将缓冲单元的下一个写入数据设置为缓冲单元，或者按照高速缓存存储器操作中的高速将高速存储信息一次性地输出到缓冲器单元 指令从外面发出。 因此，可以减少用于从/向非易失性存储装置读/写数据的数据传输的开销。
-
公开(公告)号：US07581058B2
公开(公告)日：2009-08-25
申请号：US11963913
申请日：2007-12-24
申请人： Yoshinori Takase , Keiichi Yoshida , Takashi Horii , Atsushi Nozoe , Takayuki Tamura , Tomoyuki Fujisawa , Ken Matsubara
发明人： Yoshinori Takase , Keiichi Yoshida , Takashi Horii , Atsushi Nozoe , Takayuki Tamura , Tomoyuki Fujisawa , Ken Matsubara
IPC分类号： G06F12/06
CPC分类号： G06F12/0246 , G06F12/0893 , G06F2212/2022 , G06F2212/7203 , G11C16/06 , G11C16/10 , G11C16/26 , G11C2216/22
摘要： A non-volatile storage device (1) has non-volatile memory units (FARY0 to FARY3), buffer units (BMRY0 to BMRY3) and a control unit (CNT), and the control unit can control a first access processing between an outside and the buffer unit and a second access processing between the non-volatile memory unit and the buffer unit upon receipt of directives from the outside separately from each other. The control unit can independently carry out an access control over the non-volatile memory unit and the buffer unit in accordance with the directives sent from the outside, respectively. Therefore, it is possible to set up next write data to the buffer unit simultaneously with the erase operation of the non-volatile memory unit or to output once read storage information to the buffer unit at a high speed as in a cache memory operation in accordance with the directive sent from the outside. Consequently, it is possible to reduce the overhead of a data transfer for reading/writing data from/to the non-volatile storage device.
摘要翻译： 非易失性存储设备（1）具有非易失性存储单元（FARY0至FARY3），缓冲单元（BMRY0至BMRY3）和控制单元（CNT）），控制单元可以控制外部和 所述缓冲器单元以及当从所述外部分别接收到指令时，所述非易失性存储器单元和所述缓冲器单元之间的第二访问处理。 控制单元可以分别根据从外部发送的指令独立地对非易失性存储器单元和缓冲单元执行访问控制。 因此，可以与非易失性存储器单元的擦除操作同时地将缓冲单元的下一个写入数据设置为缓冲单元，或者按照高速缓存存储器操作中的高速将高速存储信息一次性地输出到缓冲器单元 指令从外面发出。 因此，可以减少用于从/向非易失性存储装置读/写数据的数据传输的开销。
-
公开(公告)号：US07773426B2
公开(公告)日：2010-08-10
申请号：US12126285
申请日：2008-05-23
CPC分类号： G11C16/3468
摘要： Erasing is performed with respect to a nonvolatile memory cell without causing depletion halfway therethrough. A control circuit for reversibly and variably controlling the threshold voltage of the nonvolatile memory cell by electrical erasing and writing controls an erase process of performing erasing to the plurality of nonvolatile memory cells assigned to one unit in an erase operation, a first write process of performing writing to the nonvolatile memory cell exceeding a pre-write-back level before a depletion level, and a second write process of performing writing to the nonvolatile memory cell exceeding a write-back level after the first write process. Since the occurrence of depletion is suppressed by successively performing the first write process with respect to the nonvolatile memory cells which may exceed the depletion level in the erase process, erasing can be performed to the nonvolatile memory cell without causing depletion halfway therethrough.
摘要翻译： 相对于非易失性存储单元执行擦除，而不会通过其中途耗尽。 用于通过电擦除和写入可逆地和可变地控制非易失性存储单元的阈值电压的控制电路控制在擦除操作中分配给一个单元的多个非易失性存储单元执行擦除的擦除处理，执行第一写入处理 在耗尽级别之前写入超过预先写入级别的非易失性存储器单元，以及在第一写入处理之后对超过回写电平的非易失性存储单元执行写入的第二写入处理。 由于通过对于可能超过擦除处理中的耗尽电平的非易失性存储单元连续执行第一写入处理来抑制耗尽的发生，所以可以对非易失性存储单元执行擦除，而不会导致中途耗尽。
-
公开(公告)号：US07233529B2
公开(公告)日：2007-06-19
申请号：US10887077
申请日：2004-07-09
CPC分类号： G11C16/3468
摘要： Erasing is performed with respect to a nonvolatile memory cell without causing depletion halfway therethrough. A control circuit for reversibly and variably controlling the threshold voltage of the nonvolatile memory cell by electrical erasing and writing controls an erase process of performing erasing to the plurality of nonvolatile memory cells assigned to one unit in an erase operation, a first write process of performing writing to the nonvolatile memory cell exceeding a pre-write-back level before a depletion level, and a second write process of performing writing to the nonvolatile memory cell exceeding a write-back level after the first write process. Since the occurrence of depletion is suppressed by successively performing the first write process with respect to the nonvolatile memory cells which may exceed the depletion level in the erase process, erasing can be performed to the nonvolatile memory cell without causing depletion halfway therethrough.
摘要翻译： 相对于非易失性存储单元执行擦除，而不会通过其中途耗尽。 用于通过电擦除和写入可逆地和可变地控制非易失性存储单元的阈值电压的控制电路控制在擦除操作中分配给一个单元的多个非易失性存储单元执行擦除的擦除处理，执行第一写入处理 在耗尽级别之前写入超过预先写入级别的非易失性存储器单元，以及在第一写入处理之后对超过回写电平的非易失性存储单元执行写入的第二写入处理。 由于通过对于可能超过擦除处理中的耗尽电平的非易失性存储单元连续执行第一写入处理来抑制耗尽的发生，所以可以对非易失性存储单元执行擦除，而不会导致中途耗尽。
-
公开(公告)号：US07391655B2
公开(公告)日：2008-06-24
申请号：US11657025
申请日：2007-01-24
CPC分类号： G11C16/3468
摘要： Erasing is performed with respect to a nonvolatile memory cell without causing depletion halfway therethrough. A control circuit for reversibly and variably controlling the threshold voltage of the nonvolatile memory cell by electrical erasing and writing controls an erase process of performing erasing to the plurality of nonvolatile memory cells assigned to one unit in an erase operation, a first write process of performing writing to the nonvolatile memory cell exceeding a pre-write-back level before a depletion level, and a second write process of performing writing to the nonvolatile memory cell exceeding a write-back level after the first write process. Since the occurrence of depletion is suppressed by successively performing the first write process with respect to the nonvolatile memory cells which may exceed the depletion level in the erase process, erasing can be performed to the nonvolatile memory cell without causing depletion halfway therethrough.
摘要翻译： 相对于非易失性存储单元执行擦除，而不会通过其中途耗尽。 用于通过电擦除和写入可逆地和可变地控制非易失性存储单元的阈值电压的控制电路控制在擦除操作中分配给一个单元的多个非易失性存储单元执行擦除的擦除处理，执行第一写入处理 在耗尽级别之前写入超过预先写入级别的非易失性存储器单元，以及在第一写入处理之后对超过回写电平的非易失性存储单元执行写入的第二写入处理。 由于通过对于可能超过擦除处理中的耗尽电平的非易失性存储单元连续执行第一写入处理来抑制耗尽的发生，所以可以对非易失性存储单元执行擦除，而不会导致中途耗尽。
-
6.发明授权Nonvolatile memory with independent access capability to associated buffer 有权非易失性存储器，具有对相关缓冲区的独立访问能力公开(公告)号：US07334080B2
公开(公告)日：2008-02-19
申请号：US10510150
申请日：2002-11-15
申请人： Yoshinori Takase , Keiichi Yoshida , Takashi Horii , Atsushi Nozoe , Takayuki Tamura , Tomoyuki Fujisawa , Ken Matsubara
发明人： Yoshinori Takase , Keiichi Yoshida , Takashi Horii , Atsushi Nozoe , Takayuki Tamura , Tomoyuki Fujisawa , Ken Matsubara
IPC分类号： G06F12/00
CPC分类号： G06F12/0246 , G06F12/0893 , G06F2212/2022 , G06F2212/7203 , G11C16/06 , G11C16/10 , G11C16/26 , G11C2216/22
摘要： A non-volatile storage device (1) has non-volatile memory units (FARY0 to FARY3), buffer units (BMRY0 to BMRY3) and a control unit (CNT), and the control unit can control a first access processing between an outside and the buffer unit and a second access processing between the non-volatile memory unit and the buffer unit upon receipt of directives from the outside separately from each other. The control unit can independently carry out an access control over the non-volatile memory unit and the buffer unit in accordance with the directives sent from the outside, respectively. Therefore, it is possible to set up next write data to the buffer unit simultaneously with the erase operation of the non-volatile memory unit or to output once read storage information to the buffer unit at a high speed as in a cache memory operation in accordance with the directive sent from the outside. Consequently, it is possible to reduce the overhead of a data transfer for reading/writing data from/to the non-volatile storage device.
摘要翻译： 非易失性存储设备（1）具有非易失性存储单元（FARY 0至FARY 3），缓冲单元（BMRY 0至BMRY 3）和控制单元（CNT）），并且控制单元可以控制第一访问处理 在外部和缓冲单元之间以及从外部分别接收到伪指令之后的非易失性存储单元和缓冲单元之间的第二访问处理。 控制单元可以分别根据从外部发送的指令独立地对非易失性存储器单元和缓冲单元执行访问控制。 因此，可以与非易失性存储器单元的擦除操作同时地将缓冲单元的下一个写入数据设置为缓冲单元，或者按照高速缓存存储器操作中的高速将高速存储信息一次性地输出到缓冲器单元 指令从外面发出。 因此，可以减少用于从/向非易失性存储装置读/写数据的数据传输的开销。
-
公开(公告)号：US20070133278A1
公开(公告)日：2007-06-14
申请号：US11657025
申请日：2007-01-24
IPC分类号： G11C16/04
CPC分类号： G11C16/3468
摘要： Erasing is performed with respect to a nonvolatile memory cell without causing depletion halfway therethrough. A control circuit for reversibly and variably controlling the threshold voltage of the nonvolatile memory cell by electrical erasing and writing controls an erase process of performing erasing to the plurality of nonvolatile memory cells assigned to one unit in an erase operation, a first write process of performing writing to the nonvolatile memory cell exceeding a pre-write-back level before a depletion level, and a second write process of performing writing to the nonvolatile memory cell exceeding a write-back level after the first write process. Since the occurrence of depletion is suppressed by successively performing the first write process with respect to the nonvolatile memory cells which may exceed the depletion level in the erase process, erasing can be performed to the nonvolatile memory cell without causing depletion halfway therethrough.
摘要翻译： 相对于非易失性存储单元执行擦除，而不会通过其中途耗尽。 用于通过电擦除和写入可逆地和可变地控制非易失性存储单元的阈值电压的控制电路控制在擦除操作中分配给一个单元的多个非易失性存储单元执行擦除的擦除处理，执行第一写入处理 在耗尽级别之前写入超过预先写入级别的非易失性存储器单元，以及在第一写入处理之后对超过回写电平的非易失性存储单元执行写入的第二写入处理。 由于通过对于可能超过擦除处理中的耗尽电平的非易失性存储单元连续执行第一写入处理来抑制耗尽的发生，所以可以对非易失性存储单元执行擦除，而不会导致中途耗尽。
-
公开(公告)号：US20050228962A1
公开(公告)日：2005-10-13
申请号：US10510150
申请日：2002-11-15
申请人： Yoshinori Takase , Keiichi Yoshida , Takashi Horii , Atsushi Nozoe , Takayuki Tamura , Tomoyuki Fujisawa , Ken Matsubara
发明人： Yoshinori Takase , Keiichi Yoshida , Takashi Horii , Atsushi Nozoe , Takayuki Tamura , Tomoyuki Fujisawa , Ken Matsubara
CPC分类号： G06F12/0246 , G06F12/0893 , G06F2212/2022 , G06F2212/7203 , G11C16/06 , G11C16/10 , G11C16/26 , G11C2216/22
摘要： A non-volatile storage device (1) has non-volatile memory units (FARY0 to FARY3), buffer units (BMRY0 to BMRY3) and a control unit (CNT), and the control unit can control a first access processing between an outside and the buffer unit and a second access processing between the non-volatile memory unit and the buffer unit upon receipt of directives from the outside separately from each other. The control unit can independently carry out an access control over the non-volatile memory unit and the buffer unit in accordance with the directives sent from the outside, respectively. Therefore, it is possible to set up next write data to the buffer unit simultaneously with the erase operation of the non-volatile memory unit or to output once read storage information to the buffer unit at a high speed as in a cache memory operation in accordance with the directive sent from the outside. Consequently, it is possible to reduce the overhead of a data transfer for reading/writing data from/to the non-volatile storage device.
摘要翻译： 非易失性存储设备（1）具有非易失性存储单元（FARY 0至FARY 3），缓冲单元（BMRY 0至BMRY 3）和控制单元（CNT）），并且控制单元可以控制第一访问处理 在外部和缓冲单元之间以及从外部分别接收到伪指令之后的非易失性存储单元和缓冲单元之间的第二访问处理。 控制单元可以分别根据从外部发送的指令独立地对非易失性存储器单元和缓冲单元执行访问控制。 因此，可以与非易失性存储器单元的擦除操作同时地将缓冲单元的下一个写入数据设置为缓冲单元，或者按照高速缓存存储器操作中的高速将高速存储信息一次性地输出到缓冲器单元 指令从外面发出。 因此，可以减少用于从/向非易失性存储装置读/写数据的数据传输的开销。
-
公开(公告)号：US20050047215A1
公开(公告)日：2005-03-03
申请号：US10887077
申请日：2004-07-09
CPC分类号： G11C16/3468
摘要： Erasing is performed with respect to a nonvolatile memory cell without causing depletion halfway therethrough. A control circuit for reversibly and variably controlling the threshold voltage of the nonvolatile memory cell by electrical erasing and writing controls an erase process of performing erasing to the plurality of nonvolatile memory cells assigned to one unit in an erase operation, a first write process of performing writing to the nonvolatile memory cell exceeding a pre-write-back level before a depletion level, and a second write process of performing writing to the nonvolatile memory cell exceeding a write-back level after the first write process. Since the occurrence of depletion is suppressed by successively performing the first write process with respect to the nonvolatile memory cells which may exceed the depletion level in the erase process, erasing can be performed to the nonvolatile memory cell without causing depletion halfway therethrough.
摘要翻译： 相对于非易失性存储单元执行擦除，而不会通过其中途耗尽。 用于通过电擦除和写入可逆地和可变地控制非易失性存储单元的阈值电压的控制电路控制在擦除操作中分配给一个单元的多个非易失性存储单元执行擦除的擦除处理，执行第一写入处理 在耗尽级别之前写入超过预先写入级别的非易失性存储器单元，以及在第一写入处理之后对超过回写电平的非易失性存储单元执行写入的第二写入处理。 由于通过对于可能超过擦除处理中的耗尽电平的非易失性存储单元连续执行第一写入处理来抑制耗尽的发生，所以可以对非易失性存储单元执行擦除，而不会导致中途耗尽。
-
公开(公告)号：US06775185B2
公开(公告)日：2004-08-10
申请号：US10404085
申请日：2003-04-02
IPC分类号： G11C1604
CPC分类号： G11C7/1057 , G11C7/1042 , G11C7/1051 , G11C7/106 , G11C16/10 , G11C16/26
摘要： A memory bank comprises nonvolatile memory sections and two buffer sections to respectively store information of access unit of the nonvolatile memory sections. In response to the instruction of access operation, the memory bank performs data transfer between one buffer section of the memory bank and the nonvolatile memory section. In parallel to this data transfer, the memory bank also enables control of interleave operation to perform data transfer between the other buffer section of the relevant memory bank and the external side. Accordingly, high speed access can be realized by conducting in parallel the data transfer between the nonvolatile memory section and the buffer section and data transfer between the buffer section and the external side in the interleave operation. Moreover, high speed write and read access to the nonvolatile memory section can also be realized.
摘要翻译： 存储体包括非易失性存储器部分和两个缓冲器部分，用于分别存储非易失性存储器部分的存取单元的信息。 响应于访问操作的指令，存储体在存储体的一个缓冲区和非易失性存储部之间执行数据传送。 与该数据传输并行，存储体还能够进行交织操作的控制，以在相关存储体的另一个缓冲区和外部侧之间执行数据传送。 因此，可以通过并行地进行非易失性存储器部分和缓冲器部分之间的数据传输以及在交错操作中的缓冲器部分和外部侧之间的数据传送来实现高速访问。 此外，还可以实现对非易失性存储器部分的高速写入和读取访问。
-
-
-
-
-
-
-
-
-
搜索结果
26 条记录 (耗时 0.026 秒)