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    Semiconductor integrated circuit device and process for manufacturing the same
    2.
    发明授权
    Semiconductor integrated circuit device and process for manufacturing the same 失效
    半导体集成电路器件及其制造方法

    公开(公告)号：US5270944A

    公开(公告)日：1993-12-14

    申请号：US929511

    申请日：1992-08-14

    申请人： Kenichi Kuroda ,  Akinori Matsuo

    发明人： Kenichi Kuroda ,  Akinori Matsuo

    IPC分类号： H01L21/8246 ,  H01L21/8247 ,  H01L27/02 ,  H01L27/105 ,  H01L27/112 ,  G06F15/60 ,  H01L27/00

    CPC分类号： H01L27/11526 ,  H01L27/105 ,  H01L27/112 ,  H01L27/11286 ,  H01L27/11546 ,  H01L27/0207

    摘要： A method of fabrication comprising forming a semiconductor integrated circuit device LSI which has a microcomputer CPU furnished with an EPROM, determining a program for controlling the microcomputer CPU and to be set in the EPROM (performing an initial evaluation) while information is being written into and erased from the EPROM built in the semiconductor integrated circuit device LSI, and thereafter forming a semiconductor integrated circuit device LSI in which the EPROM of the first-mentioned semiconductor integrated circuit device LSI is replaced with a mask ROM. In replacing the EPROM with the mask ROM, peripheral circuits required for both the EPROM and the mask ROM have their circuit arrangements held basically the same, and specific peripheral circuits for use in only the EPROM have their circuit regions left as they are as logically inactive regions.

    摘要翻译： 一种制造方法，包括形成半导体集成电路器件LSI，其具有配备有EPROM的微型计算机CPU，确定用于控制微机CPU的程序并将其设置在EPROM中（执行初始评估），同时正在写入信息;以及 从内置于半导体集成电路器件LSI中的EPROM擦除，然后形成半导体集成电路器件LSI，其中首先提到的半导体集成电路器件LSI的EPROM被掩模ROM替代。 在使用掩模ROM替换EPROM时，EPROM和掩模ROM所需的外围电路的电路布置基本相同，仅在EPROM中使用的特定外围电路的电路区域保持不变，因为它们在逻辑上不起作用 地区。

    Nonvolatile memory device having source and drain of memory cells integrally formed with data-source lines
    4.
    发明授权
    Nonvolatile memory device having source and drain of memory cells integrally formed with data-source lines 失效
    具有与数据源线一体形成的存储单元的源极和漏极的非易失性存储器件

    公开(公告)号：US5548146A

    公开(公告)日：1996-08-20

    申请号：US470008

    申请日：1995-06-06

    申请人： Kenichi Kuroda ,  Kazuyoshi Shiba ,  Akinori Matsuo

    发明人： Kenichi Kuroda ,  Kazuyoshi Shiba ,  Akinori Matsuo

    IPC分类号： H01L21/8247 ,  G11C16/04 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

    CPC分类号： G11C16/0491 ,  H01L27/115 ,  H01L27/11526 ,  H01L27/11546 ,  H01L29/7883

    摘要： A semiconductor substrate of a first conductivity type has formed on its main surface a floating gate through a first gate insulating film and has further formed over the floating gate a control gate through a second gate insulating film. In one of a paired source and drain and across which there is provided the floating gate insulatedly above the main surface of the substrate, a semiconductor region of second conductivity type having a lower impurity concentration than that of the paired source and drain is formed in a portion of the substrate overlapping the floating gate. A nonvolatile memory device thus constructed has its writing operation carried out by extracting electrons from the floating gate to the other of the paired source and drain having a semiconductor region of the second conductivity type, having a higher impurity concentration, by an F-N tunneling of electrons flowing through the first gate insulating film and its erasing operation carried out by injecting from the paired source and drain or the semiconductor substrate into the floating gate by the F-N tunneling of electrons flowing through the first gate insulating film. Data lines or source lines can be shared between memory cells adjacent to each other in a word line direction so that the memory cells can be substantially small-sized. The writing operation and the erasing operation can be carried out by the tunnel current so that the corresponding, necessary high voltages can be generated by the internal circuits.

    摘要翻译： 第一导电类型的半导体衬底在其主表面上通过第一栅极绝缘膜形成浮栅，并且还通过第二栅极绝缘膜在浮栅上形成控制栅极。 在成对的源极和漏极中的一个中，在衬底的主表面上绝缘地设置浮置栅极，形成具有比成对的源极和漏极的杂质浓度低的第二导电类型的半导体区域 衬底的一部分与浮动栅极重叠。 如此构造的非易失性存储器件的写入操作是通过将电子从浮栅提取到具有具有较高杂质浓度的第二导电类型的半导体区域的成对源极和漏极中的另一个，通过电子的FN隧穿 流过第一栅极绝缘膜及其擦除操作，其通过由穿过第一栅极绝缘膜的电子的FN隧穿而从成对的源极和漏极或半导体衬底注入到浮置栅极中进行。 数据线或源极线可以在字线方向上彼此相邻的存储单元之间共享，使得存储器单元可以基本上小型化。 可以通过隧道电流进行写入操作和擦除操作，使得内部电路可以产生相应的必要的高电压。

    Nonvolatile memory device having buried data lines and floating gate electrode on buried data lines
    8.
    发明授权
    Nonvolatile memory device having buried data lines and floating gate electrode on buried data lines 失效
    非易失性存储器件在掩埋数据线上具有埋置的数据线和浮栅电极

    公开(公告)号：US5747849A

    公开(公告)日：1998-05-05

    申请号：US669938

    申请日：1996-06-25

    申请人： Kenichi Kuroda ,  Kazuyoshi Shiba ,  Akinori Matsuo

    发明人： Kenichi Kuroda ,  Kazuyoshi Shiba ,  Akinori Matsuo

    IPC分类号： H01L21/8247 ,  G11C16/04 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

    CPC分类号： G11C16/0491 ,  H01L27/115 ,  H01L27/11526 ,  H01L27/11546 ,  H01L29/7883

    摘要： A semiconductor substrate of a first conductivity type has formed on its main surface a floating gate through a first gate insulating film and has further formed over the floating gate a control gate through a second gate insulating film. In one of a paired source and drain and across which there is provided the floating gate insulately above the main surface of the substrate, a semiconductor region of second conductivity type having a lower impurity concentration than that of the paired source and drain is formed in a portion of the substrate overlapping the floating gate. A nonvolatile memory device thus constructed has its writing operation carried out by extracting electrons from the floating gate to the other of the paired source and drain having a semiconductor region of the second conductivity type, having a higher impurity concentration, by an F-N tunneling of electrons flowing through the first gate insulating film and its erasing operation carried out by injecting from the paired source and drain or the semiconductor substrate into the floating gate by the F-N tunneling of electrons flowing through the first gate insulating film. Data lines or source lines can be shared between memory cells adjacent to each other in a word line direction so that the memory cells can be substantially small-sized. The writing operation and the erasing operation can be carried out by the tunnel current so that the corresponding necessary high voltages can be generated by the internal circuits.

    摘要翻译： 第一导电类型的半导体衬底在其主表面上通过第一栅极绝缘膜形成浮栅，并且还通过第二栅极绝缘膜在浮栅上形成控制栅极。 在成对的源极和漏极中的一个中，在衬底的主表面上绝缘地设置浮置栅极，具有比成对的源极和漏极的杂质浓度低的第二导电类型的半导体区域形成在 衬底的一部分与浮动栅极重叠。 如此构造的非易失性存储器件的写入操作是通过将电子从浮栅提取到具有具有较高杂质浓度的第二导电类型的半导体区域的成对源极和漏极中的另一个，通过电子的FN隧穿 流过第一栅极绝缘膜及其擦除操作，其通过由穿过第一栅极绝缘膜的电子的FN隧穿而从成对的源极和漏极或半导体衬底注入到浮置栅极中进行。 数据线或源极线可以在字线方向上彼此相邻的存储单元之间共享，使得存储器单元可以基本上小型化。 可以通过隧道电流进行写入操作和擦除操作，使得内部电路可以产生相应的必要的高电压。

    Method of fabricating a second semiconductor integrated circuit device from a first semiconductor integrated circuit device
    9.
    发明授权
    Method of fabricating a second semiconductor integrated circuit device from a first semiconductor integrated circuit device 失效
    从第一半导体集成电路器件制造第二半导体集成电路器件的方法

    公开(公告)号：US5182719A

    公开(公告)日：1993-01-26

    申请号：US598774

    申请日：1990-10-18

    申请人： Kenichi Kuroda ,  Akinori Matsuo

    发明人： Kenichi Kuroda ,  Akinori Matsuo

    IPC分类号： H01L21/8247 ,  H01L27/02 ,  H01L27/105

    CPC分类号： H01L27/11526 ,  H01L27/105 ,  H01L27/11546 ,  H01L27/0207

    摘要： A method of fabricating a second semiconductor integrated circuit device includes steps of forming a first semiconductor integrated circuit device which has a microcomputer and is furnished with an EPROM; determining a program for controlling the microcomputer and to be set in the EPROM (performing an initial evaluation) while information is being written into and erased from the EPROM built in the first semiconductor integrated circuit device; and thereafter forming a second semiconductor integrated circuit device in which the EPROM of the first semiconductor integrated circuit device is replaced with a mask ROM. In replacing the EPROM with the mask ROM, the peripheral circuits required for both the EPROM and the mask ROM have their circuit arrangements held basically the same, and specific peripheral circuits for use in only the EPROM have their circuit regions left as they are as logically inactive regions.

    摘要翻译： 制造第二半导体集成电路器件的方法包括以下步骤：形成具有微计算机并具有EPROM的第一半导体集成电路器件; 确定用于控制微型计算机的程序并将其设置在EPROM中（执行初始评估），同时信息被写入并从内置于第一半导体集成电路器件中的EPROM擦除; 然后形成第二半导体集成电路器件，其中第一半导体集成电路器件的EPROM被掩模ROM代替。 在使用掩模ROM替换EPROM时，EPROM和掩模ROM所需的外围电路的电路布置基本相同，仅在EPROM中使用的特定外围电路的逻辑电路区域保持不变 非活动区域。