摘要:
A delay section delays a detected signal by less than one bit time in NRZ data. A subtraction section performs subtraction between a delayed signal and the detected signal, and outputs a resultant signal. A clock extraction section extracts, from crossing points of a subtracted signal, crossing points whose time interval is more than or equal to Tb-α and less than or equal to Tb+β (0
摘要:
A delay section delays a detected signal by less than one bit time in the NRZ data. A subtraction section performs subtraction between a delayed signal and the detected signal, and outputs a resultant signal. A clock extraction section extracts, from crossing points of a subtracted signal, crossing points whose time interval is more than or equal to (Tb−α) and less than or equal to (Tb+β) (wherein 0
摘要:
A diversity receiver carries out error detection, error correction, and data detection on each detected data string 21. An output switching unit 17 outputs a decoded data string 24 of a branch selected by a branch selector 16. The branch selector 16 selects a branch of highest priority in priority information 29 from branches of which a data detection signal 25 indicates that the data is valid and of which the number of error symbols 22 coincides with a minimum value. In the priority information 29, higher priority is assigned to a branch that includes an antenna of which the coverage is closer to that of an antenna included in a branch selected at the immediately-previous time. Thus, selected from the plurality of branches having the minimum number of error symbols 22 is the one that includes the antenna of which the coverage is closest to the coverage of the antenna included in the branch selected at the immediately-previous time. Therefore, it is possible to suppress the occurrence of misselection of a poor-quality branch, and improve a reception characteristic.
摘要:
A clock recovery circuit capable of fast and accurate clock phase locking even in the presence of frequency shift and noise. The input signal includes, in order, a preamble with an alternating bit sequence pattern, a unique word and data. A detection unit detects zero crossings and measures the time interval therebetween. A 1-interval judgment unit judges whether an interval signal is within a predetermined range, and a 2-interval judgment unit sums two adjacent interval signals and judges whether the 2-interval signal is within a predetermined range. A control unit controls a zero-crossing signal based on the judgment result and outputs a valid zero-crossing signal if judged in the affirmative. A switching unit switches between outputting the zero-crossing signal and the valid zero-crossing signal as valid phase error information based on a frame reception signal input from a frame detection unit. A clock generation unit uses the valid phase error information in generating a symbol clock.
摘要:
A clock recovery circuit capable of fast and accurate clock phase locking even in the presence of frequency shift and noise. The input signal includes, in order, a preamble with an alternating bit sequence pattern, a unique word and data. A detection unit detects zero crossings and measures the time interval therebetween. A 1-interval judgment unit judges whether an interval signal is within a predetermined range, and a 2-interval judgment unit sums two adjacent interval signals and judges whether the 2-interval signal is within a predetermined range. A control unit controls a zero-crossing signal based on the judgment result and outputs a valid zero-crossing signal if judged in the affirmative. A switching unit switches between outputting the zero-crossing signal and the valid zero-crossing signal as valid phase error information based on a frame reception signal input from a frame detection unit. A clock generation unit uses the valid phase error information in generating a symbol clock.
摘要:
A detected signal 111 contains a preamble portion which includes symbol alternations, followed by a unique word portion, and a data portion. Each time a symbol alternation is detected, a correction value calculation section 102 averages the phase shift in the detected signal 111 for a predetermined length, thereby calculating a correction value 115. The correction value determination section 103 stores a plurality of correction values 115 in a chronological order. When the unique word portion is detected, the correction value determination section 103 retains, as an effective correction value 118, a correction value which is arrived at by going back a predetermined number of correction values among the stored correction values. A phase rotation section 104 corrects the phase of the detected signal 111 by using an effective correction value 118 calculated by the correction value determination section 103.
摘要:
A demodulator 1 obtains demodulated data in a plurality of channels. Estimating portions 2a and 2b estimate and output the numbers of erroneous symbols and error locations thereof in the demodulated data. A data comparator 3 compares the demodulated data corresponding to the error locations with the demodulated data in the corresponding locations in other channels to determine whether the error location is correct, and it outputs a decision signal in response to the determination. A data selector 4 selects one of the demodulated data in the plurality of channels on the basis of the numbers of erroneous symbols and the decision signals and outputs the data as selected data. It is then possible to maintain the reliability of error detection even when a less redundant short error detecting code is used, and also to accurately select a channel of good quality even when the demodulated data in all channels contain the same extent of errors.
摘要:
A data receiving device is provided enabling a reduction in the time required for extracting a partial band signal, and capable of being easily made in a simple structure as an LSI device without requiring a plurality of analog circuits having the same characteristics. The data receiving device includes: a first sampler for sampling an in-phase signal I(t) at every predetermined sampling period and outputting the sampled in-phase signal; a second sampler for sampling a quadrature signal at every predetermined sampling period and outputting the sampled quadrature signal; a partial band extracting section structured by a complex filter for extracting partial band signals IBr, QBr from frequency components included in the sampled in-phase signal and the sampled quadrature signal; and first and second delay detection operating sections for performing a delay detecting process based on the partial band signals and outputting detection signals.
摘要:
A first signal generation section 11 generates a baseband modulation signal for an ASK modulation scheme from transmission data. A second signal generation section 12 generates a pair of baseband modulation signals for a non-ASK modulation scheme from transmission data. When performing non-ASK modulation, a switch 15 connects between an input terminal d and an output terminal and outputs the baseband modulation signals based on the non-ASK modulation. When performing ASK modulation such that the transmission power ratio of the ASK modulation scheme to the non-ASK modulation scheme is a factor of 1, a switch 14 connects between an input terminal b and an output terminal and the switch 15 connects between an input terminal c and the output terminal. When performing ASK modulation such that the transmission power ratio is a factor of 2, the switch 14 connects between an input terminal a and the output terminal and the switch 15 connects between the input terminal c and the output terminal.
摘要:
A first signal generation section 11 generates a baseband modulation signal for an ASK modulation scheme from transmission data. A second signal generation section 12 generates a pair of baseband modulation signals for a non-ASK modulation scheme from transmission data. When performing non-ASK modulation, a switch 15 connects between an input terminal d and an output terminal and outputs the baseband modulation signals based on the non-ASK modulation. When performing ASK modulation such that the transmission power ratio of the ASK modulation scheme to the non-ASK modulation scheme is a factor of 1, a switch 14 connects between an input terminal b and an output terminal and the switch 15 connects between an input terminal c and the output terminal. When performing ASK modulation such that the transmission power ratio is a factor of 2, the switch 14 connects between an input terminal a and the output terminal and the switch 15 connects between the input terminal c and the output terminal.