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    Method for reducing stress in the metallization of an integrated circuit
    1.
    发明授权
    Method for reducing stress in the metallization of an integrated circuit 失效
    降低集成电路金属化应力的方法

    公开(公告)号：US5939335A

    公开(公告)日：1999-08-17

    申请号：US3107

    申请日：1998-01-06

    申请人： Kenneth C. Arndt ,  Richard A. Conti ,  David M. Dobuzinsky ,  Laertis Economikos ,  Jeffrey P. Gambino ,  Peter D. Hoh ,  Chandrasekhar Narayan

    发明人： Kenneth C. Arndt ,  Richard A. Conti ,  David M. Dobuzinsky ,  Laertis Economikos ,  Jeffrey P. Gambino ,  Peter D. Hoh ,  Chandrasekhar Narayan

    IPC分类号： H01L21/302 ,  H01L21/3065 ,  H01L21/3205 ,  H01L21/3213 ,  H01L21/768 ,  H01L21/336

    CPC分类号： H01L21/76804 ,  H01L21/32136 ,  H01L21/76835 ,  H01L21/76885

    摘要： The stresses commonly induced in the dielectrics of integrated circuits manufactured using metal patterning methods, such as reactive ion etching (RIE) and damascene techniques, can be reduced by rounding the lower corners associated with the features which are formed as part of the integrated circuit (e.g., the interconnects) before applying the outer (i.e., passivation) layer. In connection with the formation of metal lines patterned by a metal RIE process, such corner rounding can be achieved using a two-step metal etching process including a first step which produces a vertical sidewall and a second step which tapers lower portions of the vertical sidewall or which produces a tapered spacer along the lower portions of the vertical sidewall. This results in a rounded bottom corner which improves the step coverage of the overlying dielectric, in turn eliminating the potential for cracks. For metal lines patterned by damascene, such corner rounding can be achieved using a two-step trench etching process including a first step which produces a vertical sidewall, and a second step which produces a tapered sidewall along lower portions of the vertical sidewall.

    摘要翻译： 通过使与金属图案化方法（例如反应离子蚀刻（RIE）和镶嵌技术）一起制造的集成电路的电介质中通常感应的应力可以通过将与形成为集成电路的一部分的特征相关联的下角 在施加外部（即钝化）层之前，例如，互连）。 关于通过金属RIE工艺形成的金属线的形成，可以使用包括产生垂直侧壁的第一步骤和使垂直侧壁的下部逐渐变细的第二步骤的两步金属蚀刻工艺来实现这种角圆化 或者沿着垂直侧壁的下部产生锥形间隔物。 这导致圆角的底角，其改善了上覆电介质的台阶覆盖，从而消除了裂纹的可能性。 对于由大马士革图案化的金属线，可以使用包括产生垂直侧壁的第一步骤的两步沟槽蚀刻工艺，以及沿着垂直侧壁的下部产生锥形侧壁的第二步骤来实现这种角落圆化。

    Integrated circuits having reduced stress in metallization
    2.
    发明授权
    Integrated circuits having reduced stress in metallization 失效
    集成电路在金属化中具有降低的应力

    公开(公告)号：US06208008B1

    公开(公告)日：2001-03-27

    申请号：US09260702

    申请日：1999-03-02

    申请人： Kenneth C. Arndt ,  Richard A. Conti ,  David M. Dobuzinsky ,  Laertis Economikos ,  Jeffrey P. Gambino ,  Peter D. Hoh ,  Chandrasekhar Narayan

    发明人： Kenneth C. Arndt ,  Richard A. Conti ,  David M. Dobuzinsky ,  Laertis Economikos ,  Jeffrey P. Gambino ,  Peter D. Hoh ,  Chandrasekhar Narayan

    IPC分类号： H01L2941

    CPC分类号： H01L21/76804 ,  H01L21/32136 ,  H01L21/76835 ,  H01L21/76885

    摘要： The stresses commonly induced in the dielectrics of integrated circuits manufactured using metal patterning methods, such as reactive ion etching (RIE) and damascene techniques, can be reduced by rounding the lower corners associated with the features which are formed as part of the integrated circuit (e.g., the interconnects) before applying the outer (i.e., passivation) layer. In connection with the formation of metal lines patterned by a metal RIE process, such corner rounding can be achieved using a two-step metal etching process including a first step which produces a vertical sidewall and a second step which tapers lower portions of the vertical sidewall or which produces a tapered spacer along the lower portions of the vertical sidewall. This results in a rounded bottom corner which improves the step coverage of the overlying dielectric, in turn eliminating the potential for cracks. For metal lines patterned by damascene, such corner rounding can be achieved using a two-step trench etching process including a first step which produces a vertical sidewall, and a second step which produces a tapered sidewall along lower portions of the vertical sidewall.

    摘要翻译： 通过使与金属图案化方法（例如反应离子蚀刻（RIE）和镶嵌技术）一起制造的集成电路的电介质中通常引起的应力可以通过将与形成为集成电路的一部分的特征相关联的下角 在施加外部（即钝化）层之前，例如，互连）。 关于通过金属RIE工艺形成的金属线的形成，可以使用包括产生垂直侧壁的第一步骤和使垂直侧壁的下部逐渐变细的第二步骤的两步金属蚀刻工艺来实现这种角圆化 或者沿着垂直侧壁的下部产生锥形间隔物。 这导致圆角的底角，其改善了上覆电介质的台阶覆盖，从而消除了裂纹的可能性。 对于由大马士革图案化的金属线，可以使用包括产生垂直侧壁的第一步骤的两步沟槽蚀刻工艺，以及沿着垂直侧壁的下部产生锥形侧壁的第二步骤来实现这种角落圆化。

    Manufacturing of cavity fuses on gate conductor level
    3.
    发明授权
    Manufacturing of cavity fuses on gate conductor level 失效
    在栅极导体级制造腔体保险丝

    公开(公告)号：US06274440B1

    公开(公告)日：2001-08-14

    申请号：US09282134

    申请日：1999-03-31

    申请人： Kenneth C. Arndt ,  Axel C. Brintzinger ,  Richard A. Conti ,  Donna R. Cote ,  Chandrasekhar Narayan ,  Ravikumar Ramachandran ,  Thomas S. Rupp ,  Senthil K. Srinivasan

    发明人： Kenneth C. Arndt ,  Axel C. Brintzinger ,  Richard A. Conti ,  Donna R. Cote ,  Chandrasekhar Narayan ,  Ravikumar Ramachandran ,  Thomas S. Rupp ,  Senthil K. Srinivasan

    IPC分类号： H01L21336

    CPC分类号： H01L23/5258 ,  H01L23/5256 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

    摘要： A structure and method for making a cavity fuse over a gate conductor stack. The method includes providing a semiconductor substrate having a gate conductor stack over a shallow trench isolation region, forming oxide layers on the substrate about the gate conductor stack, etching electrical contact holes through the oxide layers to the substrate, filling the electrical contact holes with a first conductive material to establish electrical contact with the gate conductor stack, etching a pattern in an uppermost oxide layer of the oxide layers, depositing a conductive layer of a second conductive material over the oxide layers and the electrical contacts, planarizing the conductive layer whereby the conductive material remains only in the pattern, anisotropically etching the oxide layers to form at least one etching hole through the oxide layers to the shallow trench isolation region, and isotropically etching at least a portion of the oxide layers about the etching hole, whereby a cavity is formed beneath at least a portion of the conductive layer pattern, the gate conductor stack comprising a fuse.

    摘要翻译： 用于在栅极导体堆叠上形成腔体熔断器的结构和方法。 该方法包括提供在浅沟槽隔离区域上具有栅极导体堆叠的半导体衬底，在栅极导体堆叠周围形成衬底周围的氧化物层，蚀刻通过氧化物层到衬底的电接触孔， 第一导电材料以与栅极导体堆叠建立电接触，蚀刻氧化物层的最上面的氧化物层中的图案，在氧化物层和电触点上沉积第二导电材料的导电层，平坦化导电层，由此 导电材料仅保留在图案中，各向异性地蚀刻氧化物层以形成通过氧化物层到浅沟槽隔离区域的至少一个蚀刻孔，并且在蚀刻孔周围各向同性蚀刻至少一部分氧化层， 形成在导电层图案的至少一部分之下，g 包括保险丝的导体堆叠。

    High throughput chemical vapor deposition process capable of filling high aspect ratio structures
    4.
    发明授权
    High throughput chemical vapor deposition process capable of filling high aspect ratio structures 失效
    能够填充高纵横比结构的高通量化学气相沉积工艺

    公开(公告)号：US6030881A

    公开(公告)日：2000-02-29

    申请号：US72759

    申请日：1998-05-05

    申请人： George D. Papasouliotis ,  Ashima B. Chakravarti ,  Richard A. Conti ,  Laertis Economikos ,  Patrick A. Van Cleemput

    发明人： George D. Papasouliotis ,  Ashima B. Chakravarti ,  Richard A. Conti ,  Laertis Economikos ,  Patrick A. Van Cleemput

    IPC分类号： C23C16/04 ,  C23C16/40 ,  C23C16/56 ,  H01L21/762

    CPC分类号： H01L21/76224 ,  C23C16/045 ,  C23C16/401 ,  C23C16/56

    摘要： A method is provided for filling high aspect ratio gaps without void formation by using a high density plasma (HDP) deposition process with a sequence of deposition and etch steps having varying etch rate-to-deposition rate (etch/dep) ratios. The first step uses an etch/dep ratio less than one to quickly fill the gap. The first step is interrupted before the opening to the gap is closed. The second step uses an etch/dep ratio greater than one to widen the gap. The second step is stopped before corners of the elements forming the gaps are exposed. These steps can be repeated until the aspect ratio of the gap is reduced so that void-free gap-fill is possible. The etch/dep ratio and duration of each step can be optimized for high throughput and high aspect ratio gap-fill capacity.

    摘要翻译： 提供了一种通过使用具有不同蚀刻速率 - 沉积速率（蚀刻/去除）比率的沉积和蚀刻步骤顺序的高密度等离子体（HDP）沉积工艺来填充高纵横比间隙而无空隙形成的方法。 第一步使用小于1的蚀刻/剥离比快速填充间隙。 第一步在打开间隙之前中断。 第二步使用大于1的蚀刻/剥离比来扩大间隙。 在形成间隙的元件的角部暴露之前停止第二步骤。 可以重复这些步骤，直到间隙的纵横比减小，使得无空隙间隙填充成为可能。 可以优化每个步骤的蚀刻/剥离比和持续时间，以实现高通量和高纵横比填充间隙。

    Low temperature LPCVD PSG/BPSG process
    5.
    发明授权
    Low temperature LPCVD PSG/BPSG process 失效
    低温LPCVD PSG / BPSG工艺

    公开(公告)号：US06429149B1

    公开(公告)日：2002-08-06

    申请号：US09511394

    申请日：2000-02-23

    申请人： Ashima B. Chakravarti ,  Richard A. Conti ,  Laertis Economikos ,  Byeongju Park

    发明人： Ashima B. Chakravarti ,  Richard A. Conti ,  Laertis Economikos ,  Byeongju Park

    IPC分类号： H01L2131

    CPC分类号： H01L21/02271 ,  C23C16/401 ,  H01L21/02129 ,  H01L21/02164 ,  H01L21/02337 ,  H01L21/31625

    摘要： A disclosed process use low pressure chemical vapor deposition (LPCVD) of doped oxide film on a substrate. The process includes the steps of providing a substrate in an LPCVD reactor and flowing BTBAS and oxygen into the LPCVD reactor to react on the substrate to deposit an oxide film on the substrate. A doped precursor is flowed into the LPCVD reactor to dope the oxide film as it is deposited on the substrate. This process produces doped oxide film at a relatively low LPCVD reaction temperature.

    摘要翻译： 所公开的方法使用在衬底上的掺杂氧化物膜的低压化学气相沉积（LPCVD）。 该方法包括以下步骤：在LPCVD反应器中提供衬底并将BTBAS和氧气流入LPCVD反应器以在衬底上反应以在衬底上沉积氧化物膜。 掺杂的前体流入LPCVD反应器以在氧化膜沉积在衬底上时掺杂氧化膜。 该方法在相对低的LPCVD反应温度下产生掺杂的氧化物膜。

    Directional CVD process with optimized etchback
    6.
    发明授权
    Directional CVD process with optimized etchback 有权
    具有优化回蚀的定向CVD工艺

    公开(公告)号：US06335261B1

    公开(公告)日：2002-01-01

    申请号：US09584355

    申请日：2000-05-31

    申请人： Wesley Natzle ,  Richard A. Conti ,  Laertis Economikos ,  Thomas Ivers ,  George D. Papasouliotis

    发明人： Wesley Natzle ,  Richard A. Conti ,  Laertis Economikos ,  Thomas Ivers ,  George D. Papasouliotis

    IPC分类号： H01L2100

    CPC分类号： H01L21/76224 ,  C23C16/045 ,  H01L21/30655 ,  H01L21/32136 ,  H01L21/764

    摘要： A method is described for filling a high-aspect-ratio feature, in which compatible deposition and etching steps are performed in a sequence. The feature is formed as an opening in a substrate having a surface; a fill material is deposited at the bottom of the feature and on the surface of the substrate; deposition on the surface adjacent the feature causes formation of an overhang structure partially blocking the opening. The fill material is then reacted with a reactant to form a solid reaction product having a greater specific volume than the fill material. The overhang structure is thus converted into a reaction product structure blocking the opening. The reaction product (including the reaction product structure) is then desorbed, thereby exposing unreacted fill material at the bottom of the feature. The depositing and reacting steps may be repeated, with a final depositing step to fill the feature. Each sequence of depositing, reacting and desorbing reduces the aspect ratio of the feature.

    摘要翻译： 描述了一种用于填充高纵横比特征的方法，其中以顺序执行相容的沉积和蚀刻步骤。 该特征形成为具有表面的基板中的开口; 填充材料沉积在特征的底部和基底的表面上; 在与特征相邻的表面上的沉积导致形成部分阻挡开口的突出结构。 然后将填充材料与反应物反应以形成具有比填充材料更大的比体积的固体反应产物。 因此，突出结构被转化成阻塞开口的反应产物结构。 然后将反应产物（包括反应产物结构）解吸，从而在特征底部暴露未反应的填充材料。 沉积和反应步骤可以重复，最终沉积步骤以填补该特征。 沉积，反应和解吸的每个顺序降低了特征的纵横比。

    Method of eliminating a critical mask using a blockout mask and a resulting semiconductor structure
    9.
    发明授权
    Method of eliminating a critical mask using a blockout mask and a resulting semiconductor structure 失效
    使用阻挡掩模和所得半导体结构消除临界掩模的方法

    公开(公告)号：US06232222B1

    公开(公告)日：2001-05-15

    申请号：US09395418

    申请日：1999-09-14

    申请人： Michael Armacost ,  Richard A. Conti ,  Jeffrey P. Gambino ,  Jeremy K. Stephens

    发明人： Michael Armacost ,  Richard A. Conti ,  Jeffrey P. Gambino ,  Jeremy K. Stephens

    IPC分类号： H01L214763

    CPC分类号： H01L21/76897 ,  H01L21/31144 ,  H01L27/10873 ,  H01L27/10894

    摘要： A method of forming a semiconductor structure may include forming a semiconductor substrate having an array region and a support region, forming a semiconductor substrate and a gate stack over the support region of the substrate and applying a critical mask over the support region and the array region. The critical mask may have a first opening at an area corresponding to the array region and a second opening at an area corresponding to the support region. Contact holes may be formed in a glass layer at areas corresponding to the first and second opening. After removing the critical mask, a first blockout mask may be applied over the array region and a first conductive type dopant may be added to exposed polysilicon corresponding to openings of the blockout mask or gate contacts may be formed.

    摘要翻译： 形成半导体结构的方法可以包括形成具有阵列区域和支撑区域的半导体衬底，在衬底的支撑区域上形成半导体衬底和栅叠层，并在衬底区域和阵列区域上施加临界掩模 。 临界掩模可以在对应于阵列区域的区域处具有第一开口，并且在对应于支撑区域的区域处具有第二开口。 可以在对应于第一和第二开口的区域的玻璃层中形成接触孔。 在去除临界掩模之后，可以在阵列区域上施加第一堵塞掩模，并且可以形成第一导电型掺杂剂，以对应于封闭掩模的开口或栅极触点形成对应于暴露的多晶硅。