公开(公告)号：US06344129B1

公开(公告)日：2002-02-05

申请号：US09418197

申请日：1999-10-13

申请人： Kenneth P. Rodbell ,  Panayotis C. Andricacos ,  Cyril Cabral, Jr. ,  Lynne M. Gignac ,  Cyprian E. Uzoh ,  Peter S. Locke

发明人： Kenneth P. Rodbell ,  Panayotis C. Andricacos ,  Cyril Cabral, Jr. ,  Lynne M. Gignac ,  Cyprian E. Uzoh ,  Peter S. Locke

IPC分类号： C25D500

CPC分类号： C25D5/10 ,  C25D3/38 ,  C25D5/00 ,  C25D7/123 ,  C25D21/02 ,  H05K3/423

摘要： A method for plating copper conductors on an electronic substrate and devices formed are disclosed. In the method, an electroplating copper bath that is filled with an electroplating solution kept at a temperature between about 0° C. and about 18° C. is first provided. A copper layer on the electronic substrate immersed in the electroplating solution is then plated either in a single step or in a dual-step deposition process. The dual-step deposition process is more suitable for depositing copper conductors in features that have large aspect ratios, such as a via hole in a dual damascene structure having an aspect ratio of diameter/depth of more than ⅓ or as high as {fraction (1/10)}. Various electroplating parameters are utilized to provide a short resistance transient in either the single step deposition or the dual-step deposition process. These parameters include the bath temperature, the bath agitation, the additive concentration in the plating bath, the plating current density utilized, the deposition rate of the copper film and the total thickness of the copper film deposited.

摘要翻译： 公开了一种在电子基板上镀铜导体的方法和形成的器件。 在该方法中，首先提供填充有保持在约0℃至约18℃之间的温度的电镀溶液的电镀铜浴。 然后将浸在电镀溶液中的电子基板上的铜层以单步骤或双步沉积工艺进行镀覆。 双步沉积方法更适合于在具有大纵横比的特征中沉积铜导体，例如双镶嵌结构中的通孔，其直径/深度的纵横比大于1/3或高达{分数（ 1/10）}。 各种电镀参数用于在单步沉积或双步沉积工艺中提供短电阻瞬变。 这些参数包括浴温度，浴液搅拌，镀浴中的添加剂浓度，所用的电镀电流密度，铜膜的沉积速率和沉积的铜膜的总厚度。

公开(公告)号：US06979393B2

公开(公告)日：2005-12-27

申请号：US10055134

申请日：2002-01-22

申请人： Kenneth P. Rodbell ,  Panayotis C. Andricacos ,  Cyril Cabral, Jr. ,  Lynne M. Gignac ,  Cyprian E. Uzoh ,  Peter S. Locke

发明人： Kenneth P. Rodbell ,  Panayotis C. Andricacos ,  Cyril Cabral, Jr. ,  Lynne M. Gignac ,  Cyprian E. Uzoh ,  Peter S. Locke

IPC分类号： C25D3/38 ,  C25D5/00 ,  C25D5/10 ,  C25D7/12 ,  H05K3/42 ,  C25D5/02

CPC分类号： C25D5/10 ,  C25D3/38 ,  C25D5/00 ,  C25D7/123 ,  C25D21/02 ,  H05K3/423

摘要： A method for plating copper conductors on an electronic substrate and devices formed are disclosed. In the method, an electroplating copper bath that is filled with an electroplating solution kept at a temperature between about 0° C. and about 18° C. is first provided. A copper layer on the electronic substrate immersed in the electroplating solution is then plated either in a single step or in a dual-step deposition process. The dual-step deposition process is more suitable for depositing copper conductors in features that have large aspect ratios, such as a via hole in a dual damascene structure having an aspect ratio of diameter/depth of more than ⅓ or as high as 1/10. Various electroplating parameters are utilized to provide a short resistance transient in either the single step deposition or the dual-step deposition process. These parameters include the bath temperature, the bath agitation, the additive concentration in the plating bath, the plating current density utilized, the deposition rate of the copper film and the total thickness of the copper film deposited.

摘要翻译： 公开了一种在电子基板上镀铜导体的方法和形成的器件。 在该方法中，首先提供填充有保持在约0℃至约18℃之间的温度的电镀溶液的电镀铜浴。 然后将浸在电镀溶液中的电子基板上的铜层以单步骤或双步沉积工艺进行镀覆。 双步沉积方法更适合于在具有大纵横比的特征中沉积铜导体，例如具有大于1/3或高达1的直径/深度的纵横比的双镶嵌结构中的通孔 / 10。 各种电镀参数用于在单步沉积或双步沉积过程中提供短电阻瞬变。 这些参数包括浴温度，浴液搅拌，镀浴中的添加剂浓度，所用的电镀电流密度，铜膜的沉积速率和沉积的铜膜的总厚度。

公开(公告)号：US08129267B2

公开(公告)日：2012-03-06

申请号：US12052881

申请日：2008-03-21

申请人： Cyril Cabral, Jr. ,  K. Paul Muller ,  Kenneth P. Rodbell

发明人： Cyril Cabral, Jr. ,  K. Paul Muller ,  Kenneth P. Rodbell

IPC分类号： H01L21/4763

CPC分类号： H01L23/5223 ,  H01L23/3192 ,  H01L23/53238 ,  H01L23/556 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/73 ,  H01L24/81 ,  H01L2224/02166 ,  H01L2224/03831 ,  H01L2224/0401 ,  H01L2224/05027 ,  H01L2224/05558 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/0603 ,  H01L2224/06051 ,  H01L2224/10125 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/13007 ,  H01L2224/13028 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13147 ,  H01L2224/13487 ,  H01L2224/1403 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/73204 ,  H01L2224/81447 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01082 ,  H01L2924/01084 ,  H01L2924/01088 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2224/05552 ,  H01L2924/00

摘要： An alpha particle blocking structure and method of making the structure. The structure includes: a semiconductor substrate; a set of interlevel dielectric layers stacked from a lowermost interlevel dielectric layer closest to the substrate to a uppermost interlevel dielectric layer furthest from the substrate, each interlevel dielectric layer of the set of interlevel dielectric layers including electrically conductive wires, top surfaces of the wires substantially coplanar with top surfaces of corresponding interlevel dielectric layers; an electrically conductive tot final pad contacting a wire pad of the uppermost interlevel dielectric layer; an electrically conductive plating base layer contacting a top surface of the terminal pad; and a copper block on the plating base layer.

摘要翻译： 一种α粒子阻挡结构及其制造方法。 该结构包括：半导体衬底; 一组层间电介质层，从最靠近衬底的最下层的层间电介质层堆叠到距离衬底最远的最上层的层间电介质层，层间电介质层组中的每个层间电介质层包括导电线，电线的顶表面基本上 与对应的层间电介质层的顶表面共面; 接触最上面的层间电介质层的焊盘的导电的最终焊盘; 与所述端子焊盘的顶表面接触的导电电镀基层; 以及镀覆基底层上的铜块。

公开(公告)号：US08008199B2

公开(公告)日：2011-08-30

申请号：US12869113

申请日：2010-08-26

申请人： Brett C. Baker-O'Neal ,  Cyril Cabral, Jr. ,  Qiang Huang ,  Kenneth P. Rodbell

发明人： Brett C. Baker-O'Neal ,  Cyril Cabral, Jr. ,  Qiang Huang ,  Kenneth P. Rodbell

IPC分类号： H01L21/44 ,  H01L21/4763

CPC分类号： H01L21/76877 ,  H01L21/76873 ,  H01L23/53233 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： Cobalt is added to a copper seed layer, a copper plating layer, or a copper capping layer in order to modify the microstructure of copper lines and vias. The cobalt can be in the form of a copper-cobalt alloy or as a very thin cobalt layer. The grain boundaries configured in bamboo microstructure in the inventive metal interconnect structure shut down copper grain boundary diffusion. The composition of the metal interconnect structure after grain growth contains from about 1 ppm to about 10% of cobalt in atomic concentration. Grain boundaries extend from a top surface of a copper-cobalt alloy line to a bottom surface of the copper-cobalt alloy line, and are separated from any other grain boundary by a distance greater than a width of the copper-cobalt alloy line.

摘要翻译： 为了改变铜线和通孔的微观结构，将钴添加到铜种子层，铜镀层或铜覆盖层。 钴可以是铜 - 钴合金的形式或作为非常薄的钴层。 本发明金属互连结构中竹结构中晶界的结构关闭了铜晶界扩散。 晶粒生长后的金属互连结构的组成含有约1ppm至约10原子浓度的钴。 晶粒边界从铜 - 钴合金线的顶表面延伸到铜 - 钴合金线的底表面，并且与任何其它晶界分开大于铜 - 钴合金线的宽度的距离。

公开(公告)号：US07843063B2

公开(公告)日：2010-11-30

申请号：US12031103

申请日：2008-02-14

申请人： Brett C. Baker-O'Neal ,  Cyril Cabral, Jr. ,  Qiang Huang ,  Kenneth P. Rodbell

发明人： Brett C. Baker-O'Neal ,  Cyril Cabral, Jr. ,  Qiang Huang ,  Kenneth P. Rodbell

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L21/76877 ,  H01L21/76873 ,  H01L23/53233 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： Cobalt is added to a copper seed layer, a copper plating layer, or a copper capping layer in order to modify the microstructure of copper lines and vias. The cobalt can be in the form of a copper-cobalt alloy or as a very thin cobalt layer. The grain boundaries configured in bamboo microstructure in the inventive metal interconnect structure shut down copper grain boundary diffusion. The composition of the metal interconnect structure after grain growth contains from about 1 ppm to about 10% of cobalt in atomic concentration. Grain boundaries extend from a top surface of a copper-cobalt alloy line to a bottom surface of the copper-cobalt alloy line, and are separated from any other grain boundary by a distance greater than a width of the copper-cobalt alloy line.

摘要翻译： 为了改变铜线和通孔的微观结构，将钴添加到铜种子层，铜镀层或铜覆盖层。 钴可以是铜 - 钴合金的形式或作为非常薄的钴层。 本发明金属互连结构中竹结构中晶界的结构关闭了铜晶界扩散。 晶粒生长后的金属互连结构的组成含有约1ppm至约10原子浓度的钴。 晶粒边界从铜 - 钴合金线的顶表面延伸到铜 - 钴合金线的底表面，并且与任何其它晶界分开大于铜 - 钴合金线的宽度的距离。

公开(公告)号：US08772161B2

公开(公告)日：2014-07-08

申请号：US13205063

申请日：2011-08-08

申请人： Cyril Cabral, Jr. ,  Gregory M. Fritz ,  Christian Lavoie ,  Conal E. Murray ,  Kenneth P Rodbell

发明人： Cyril Cabral, Jr. ,  Gregory M. Fritz ,  Christian Lavoie ,  Conal E. Murray ,  Kenneth P Rodbell

IPC分类号： H01L21/44

CPC分类号： H01L29/665 ,  H01L21/28518 ,  H01L21/76828 ,  H01L21/76886 ,  H01L21/823814 ,  H01L21/823842 ,  H01L21/823871 ,  H01L21/84 ,  H01L27/1203

摘要： A method for modifying the chemistry or microstructure of silicon-based technology via an annealing process is provided. The method includes depositing a reactive material layer within a selected proximity to an interconnect, igniting the reactive material layer, and annealing the interconnect via heat transferred from the ignited reactive material layer. The method can also be implemented in connection with a silicide/silicon interface as well as a zone of silicon-based technology.

摘要翻译： 提供了一种通过退火工艺改性硅基技术的化学或微结构的方法。 该方法包括将反应性材料层沉积在选定的互连附近，点燃反应性材料层，以及通过从点燃的反应性材料层传递的热量使互连件退火。 该方法还可以结合硅化物/硅界面以及硅基技术的区域来实现。

公开(公告)号：US08293643B2

公开(公告)日：2012-10-23

申请号：US12819634

申请日：2010-06-21

申请人： Cyril Cabral, Jr. ,  John M. Cotte ,  Kathryn C. Fisher ,  Laura L. Kosbar ,  Christian Lavoie ,  Zhu Liu ,  Kenneth P. Rodbell ,  Xiaoyan Shao

发明人： Cyril Cabral, Jr. ,  John M. Cotte ,  Kathryn C. Fisher ,  Laura L. Kosbar ,  Christian Lavoie ,  Zhu Liu ,  Kenneth P. Rodbell ,  Xiaoyan Shao

IPC分类号： H01L21/477

CPC分类号： H01L21/28518 ,  H01L21/76841 ,  H01L23/53238 ,  H01L31/022408 ,  H01L31/022425 ,  H01L2924/0002 ,  Y02E10/50 ,  H01L2924/00

摘要： A semiconductor device or a photovoltaic cell having a contact structure, which includes a silicon (Si) substrate; a metal alloy layer deposited on the silicon substrate; a metal silicide layer and a diffusion layer formed simultaneously from thermal annealing the metal alloy layer; and a metal layer deposited on the metal silicide and barrier layers.

摘要翻译： 具有接触结构的半导体器件或光电池，其包括硅（Si）衬底; 沉积在硅衬底上的金属合金层; 金属硅化物层和由金属合金层热退火同时形成的扩散层; 以及沉积在金属硅化物和阻挡层上的金属层。

公开(公告)号：US07381635B2

公开(公告)日：2008-06-03

申请号：US11183647

申请日：2005-07-18

申请人： Cyril Cabral, Jr. ,  Michael S. Gordon ,  Kenneth P. Rodbell

发明人： Cyril Cabral, Jr. ,  Michael S. Gordon ,  Kenneth P. Rodbell

IPC分类号： H01L21/44

CPC分类号： H01L23/556 ,  H01L21/76801 ,  H01L21/76834 ,  H01L21/76838 ,  H01L23/5329 ,  H01L23/53295 ,  H01L23/585 ,  H01L24/03 ,  H01L24/05 ,  H01L24/12 ,  H01L24/16 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05006 ,  H01L2224/05554 ,  H01L2224/05572 ,  H01L2224/05599 ,  H01L2224/13007 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/16 ,  H01L2224/451 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01044 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01055 ,  H01L2924/01057 ,  H01L2924/01063 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/01084 ,  H01L2924/01092 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/10253 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/15312 ,  H01L2924/15787 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30107 ,  H01L2924/3025 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2224/05552

摘要： A structure and a method for reduction of soft error rates in integrated circuits. The structure including: a semiconductor substrate; and a stack of one or more wiring levels stacked from a lowermost wiring level to an uppermost wiring level, the lowermost wiring level nearer the semiconductor substrate than the uppermost wiring level; and an alpha particle blocking layer on a top surface of the uppermost wiring level of the one or more wiring levels, the blocking layer comprising metal wires and a dielectric material, the blocking layer having a combination of a thickness of the blocking layer and a volume percent of metal wires in the blocking layer sufficient to stop a predetermined percentage of alpha particles of a selected energy or less striking the blocking layer from penetrating into the stack of one or more wiring levels or the substrate.

摘要翻译： 降低集成电路中软错误率的结构和方法。 该结构包括：半导体衬底; 以及从最下布线电平堆叠到最上布线电平的一个或多个布线电平的堆叠，比最上布线电平更靠近半导体基板的最下布线电平; 以及在所述一个或多个布线层的最上布线层的顶表面上的α粒子阻挡层，所述阻挡层包括金属线和介电材料，所述阻挡层具有阻挡层的厚度和体积 阻挡层中的金属线的百分比足以阻止预定百分比的选定能量的α粒子或更少的击穿阻挡层的金属线穿透到一个或多个布线层或衬底的堆叠中。

公开(公告)号：US08247271B2

公开(公告)日：2012-08-21

申请号：US12200352

申请日：2008-08-28

申请人： Paul Stephen Andry ,  Cyril Cabral, Jr. ,  Kenneth P. Rodbell ,  Robert L. Wisnieff

发明人： Paul Stephen Andry ,  Cyril Cabral, Jr. ,  Kenneth P. Rodbell ,  Robert L. Wisnieff

IPC分类号： H01L21/30

CPC分类号： H01L23/556 ,  H01L21/304 ,  H01L21/481 ,  H01L24/11 ,  H01L24/29 ,  H01L24/81 ,  H01L24/83 ,  H01L2224/16 ,  H01L2224/16113 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/29111 ,  H01L2224/73204 ,  H01L2224/81801 ,  H01L2224/83801 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/2064 ,  H01L2924/3025 ,  H01L2224/13111 ,  H01L2924/00014

摘要： A structure fabrication method. First, an integrated circuit including N chip electric pads is provided electrically connected to a plurality of devices on the integrated circuit. Then, an interposing shield having a top side and a bottom side and having N electric conductors in the interposing shield is provided being exposed to a surrounding ambient at the top side but not at the bottom side. Next, the integrated circuit is bonded to the top side of the interposing shield such that the N chip electric pads are in electrical contact with the N electric conductors. Next, the bottom side of the interposing shield is polished so as to expose the N electric conductors to the surrounding ambient at the bottom side of the interposing shield. Then, N solder bumps are formed on the polished bottom side of the interposing shield and in electrical contact with the N electric conductors.

摘要翻译： 一种结构制造方法。 首先，将包括N个芯片电焊盘的集成电路电连接到集成电路上的多个器件。 然后，设置具有顶侧和底侧并且在中间屏蔽中具有N个电导体的插入式屏蔽件，其暴露于顶侧周围的环境而不是在底侧。 接下来，集成电路接合到中间屏蔽的顶侧，使得N个芯片电极焊盘与N个导电体电接触。 接下来，对中介屏蔽的底面进行抛光，以将N根电导体暴露于插入式屏蔽的底侧周围环境。 然后，在中间屏蔽的抛光底面上形成N个焊料凸块，并与N个导电体电接触。

公开(公告)号：US08212218B2

公开(公告)日：2012-07-03

申请号：US12627076

申请日：2009-11-30

申请人： Cyril Cabral, Jr. ,  Michael S. Gordon ,  Steven J. Koester ,  Conal E. Murray ,  Kenneth P. Rodbell ,  Stephen M. Rossnagel ,  Robert L. Wisnieff ,  Jeng-bang Yau

发明人： Cyril Cabral, Jr. ,  Michael S. Gordon ,  Steven J. Koester ,  Conal E. Murray ,  Kenneth P. Rodbell ,  Stephen M. Rossnagel ,  Robert L. Wisnieff ,  Jeng-bang Yau

IPC分类号： G01T1/02

CPC分类号： G01T1/026

摘要： A system for determining an amount of radiation includes a dosimeter configured to receive the amount of radiation, the dosimeter comprising a circuit having a resonant frequency, such that the resonant frequency of the circuit changes according to the amount of radiation received by the dosimeter, the dosimeter further configured to absorb RF energy at the resonant frequency of the circuit; a radio frequency (RF) transmitter configured to transmit the RF energy at the resonant frequency to the dosimeter; and a receiver configured to determine the resonant frequency of the dosimeter based on the absorbed RF energy, wherein the amount of radiation is determined based on the resonant frequency.

摘要翻译： 用于确定辐射量的系统包括配置成接收辐射量的剂量计，该剂量计包括具有谐振频率的电路，使得电路的谐振频率根据剂量计接收的辐射量而改变， 剂量计还被配置为吸收电路的谐振频率处的RF能量; 射频（RF）发射器，被配置为以共振频率将所述RF能量传输到所述剂量计; 以及接收器，被配置为基于所吸收的RF能量来确定所述剂量计的谐振频率，其中所述辐射量基于所述谐振频率来确定。