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    Method of Manufacturing High Breakdown Voltage Semiconductor Device
    7.
    发明申请
    Method of Manufacturing High Breakdown Voltage Semiconductor Device 审中-公开
    制造高击穿电压半导体器件的方法

    公开(公告)号：US20120178223A1

    公开(公告)日：2012-07-12

    申请号：US13235193

    申请日：2011-09-16

    申请人： Yoshinosuke Nishijo ,  Hironobu Shibata ,  Hiroshi Ishibashi

    发明人： Yoshinosuke Nishijo ,  Hironobu Shibata ,  Hiroshi Ishibashi

    IPC分类号： H01L21/331

    CPC分类号： H01L29/66348 ,  H01L21/268 ,  H01L29/7397

    摘要： According to one embodiment, a method of manufacturing a semiconductor device includes a polishing step, a first amorphous silicon film formation step, a single crystallization step and a buffer layer formation step. In the first amorphous silicon film formation step, a first amorphous silicon film of the first conductivity type is formed on the polished back surface of the high-resistance layer, the first amorphous silicon film having a higher impurity concentration than the high-resistance layer. In the single crystallization step, the first amorphous silicon film is single-crystallized by irradiating the first amorphous silicon film with a first laser. In the buffer layer formation step, the formation and single-crystallization of the first amorphous silicon film are repeated more than once to form a buffer layer of the first conductivity type on the back surface of the high-resistance layer, the buffer layer having a higher impurity concentration than the high-resistance layer.

    摘要翻译： 根据一个实施例，制造半导体器件的方法包括抛光步骤，第一非晶硅膜形成步骤，单一结晶步骤和缓冲层形成步骤。 在第一非晶硅膜形成步骤中，第一导电类型的第一非晶硅膜形成在高电阻层的抛光后表面上，第一非晶硅膜的杂质浓度高于高电阻层。 在单结晶化步骤中，通过用第一激光照射第一非晶硅膜来使第一非晶硅膜单晶化。 在缓冲层形成步骤中，第一非晶硅膜的形成和单晶化重复多于一次以在高电阻层的背面上形成第一导电类型的缓冲层，缓冲层具有 杂质浓度高于高电阻层。

    Trench gate semiconductor device with a reduction in switching loss
    8.
    发明授权
    Trench gate semiconductor device with a reduction in switching loss 失效
    沟槽栅极半导体器件具有降低的开关损耗

    公开(公告)号：US07268392B2

    公开(公告)日：2007-09-11

    申请号：US11062838

    申请日：2005-02-23

    申请人： Hironobu Shibata ,  Noboru Matsuda

    发明人： Hironobu Shibata ,  Noboru Matsuda

    IPC分类号： H01L29/94 ,  H01L21/336

    CPC分类号： H01L29/7813 ,  H01L29/0623 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/66348 ,  H01L29/66734 ,  H01L29/7397

    摘要： A semiconductor device comprises: a first semiconductor region of a first conductivity type; a second semiconductor region of a second conductivity type provided on the first semiconductor region; a trench formed in the second semiconductor region; a thick gate insulating film selectively provided in a center area of a bottom surface of the trench; a thin gate insulating film provided along a periphery of the bottom surface and on a sidewall of the trench; a third semiconductor region of the first conductivity type that is selectively provided below the thin gate insulating film provided along the periphery of the bottom surface of the trench and that extends to the first semiconductor region; a fourth semiconductor region of the first conductivity type selectively provided in the surface of the second semiconductor region; and a gate electrode filling the trench via the gate insulating film.

    摘要翻译： 半导体器件包括：第一导电类型的第一半导体区域; 设置在第一半导体区域上的第二导电类型的第二半导体区域; 形成在第二半导体区域中的沟槽; 选择性地设置在沟槽的底面的中心区域的厚栅极绝缘膜; 沿着所述底表面的周边和所述沟槽的侧壁上设置的薄栅极绝缘膜; 第一导电类型的第三半导体区域，其被选择性地设置在沿着沟槽的底表面的周边设置并延伸到第一半导体区域的薄栅极绝缘膜的下方; 选择性地设置在第二半导体区域的表面中的第一导电类型的第四半导体区域; 以及通过栅极绝缘膜填充沟槽的栅电极。

    Film bulk acoustic resonator and method for manufacturing the same
    9.
    发明申请
    Film bulk acoustic resonator and method for manufacturing the same 审中-公开
    薄膜体声波谐振器及其制造方法

    公开(公告)号：US20070057599A1

    公开(公告)日：2007-03-15

    申请号：US11430053

    申请日：2006-05-09

    申请人： Takako Motai ,  Hironobu Shibata

    发明人： Takako Motai ,  Hironobu Shibata

    IPC分类号： H01L41/08

    CPC分类号： H03H3/02 ,  H03H9/105 ,  H03H9/173 ,  H03H9/174 ,  H03H2003/021 ,  H03H2003/023

    摘要： A film bulk acoustic resonator includes a substrate having a through hole which is defined by an opening on a bottom surface of the substrate opposed to a top surface thereof. A width of the opening is larger than that at the top surface. A bottom electrode is provided above the through hole and extended over the top surface. A piezoelectric film is disposed on the bottom electrode. A top electrode is disposed on the piezoelectric film so as to face the bottom electrode. A sealing plate is inserted from the bottom surface into the through hole so as to seal the opening.

    摘要翻译： 薄膜体声波谐振器包括具有通孔的基板，该通孔由基板的与其顶面相对的底面上的开口限定。 开口的宽度大于顶面宽度。 底部电极设置在通孔上方并在顶表面上延伸。 压电膜设置在底部电极上。 顶部电极以与底部电极相对的方式设置在压电膜上。 将密封板从底面插入通孔以密封开口。

    Semiconductor device and method of manufacturing same
    10.
    发明申请
    Semiconductor device and method of manufacturing same 失效
    半导体装置及其制造方法

    公开(公告)号：US20060086972A1

    公开(公告)日：2006-04-27

    申请号：US11062838

    申请日：2005-02-23

    申请人： Hironobu Shibata ,  Noboru Matsuda

    发明人： Hironobu Shibata ,  Noboru Matsuda

    IPC分类号： H01L29/94

    CPC分类号： H01L29/7813 ,  H01L29/0623 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/66348 ,  H01L29/66734 ,  H01L29/7397

    摘要： A semiconductor device comprises: a first semiconductor region of a first conductivity type; a second semiconductor region of a second conductivity type provided on the first semiconductor region; a trench formed in the second semiconductor region; a thick gate insulating film selectively provided in a center area of a bottom surface of the trench; a thin gate insulating film provided along a periphery of the bottom surface and on a sidewall of the trench; a third semiconductor region of the first conductivity type that is selectively provided below the thin gate insulating film provided along the periphery of the bottom surface of the trench and that extends to the first semiconductor region; a fourth semiconductor region of the first conductivity type selectively provided in the surface of the second semiconductor region; and a gate electrode filling the trench via the gate insulating film.

    摘要翻译： 半导体器件包括：第一导电类型的第一半导体区域; 设置在第一半导体区域上的第二导电类型的第二半导体区域; 形成在第二半导体区域中的沟槽; 选择性地设置在沟槽的底面的中心区域的厚栅极绝缘膜; 沿着所述底表面的周边和所述沟槽的侧壁上设置的薄栅极绝缘膜; 第一导电类型的第三半导体区域，其被选择性地设置在沿着沟槽的底表面的周边设置并延伸到第一半导体区域的薄栅极绝缘膜的下方; 选择性地设置在第二半导体区域的表面中的第一导电类型的第四半导体区域; 以及通过栅极绝缘膜填充沟槽的栅电极。