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公开(公告)号：US06954916B2
公开(公告)日：2005-10-11
申请号：US10604179
申请日：2003-06-30
CPC分类号： G06F17/5022
摘要： A method and system for simulating an integrated circuit. The method includes the steps of performing a timing analysis of the circuits to ensure that they meet specified timing criteria, performing soft error analysis of the circuits to determine whether they meet specified soft error criteria, and improving those circuits that fail the soft error analysis to improve their resistance to soft errors and having no degradation on timing. Preferably, the improving step includes the step of improving those circuits that fail the soft error analysis by either having an additional voltage source or altering the capacitance of the circuits.
摘要翻译： 一种用于模拟集成电路的方法和系统。 该方法包括以下步骤：执行电路的定时分析，以确保它们满足规定的时序准则，执行电路的软错误分析，以确定它们是否符合指定的软错误标准，以及改进那些无法通过软错误分析的电路 提高其对软错误的抵抗力，并且在时序上没有劣化。 优选地，改进步骤包括通过具有附加电压源或改变电路的电容来改进不能通过软误差分析的那些电路的步骤。
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公开(公告)号：US07642813B2
公开(公告)日：2010-01-05
申请号：US11850857
申请日：2007-09-06
申请人： Kerry Bernstein , Philip G. Emma , John A. Fifield , Paul D. Kartschoke , William A. Klaasen , Norman J. Rohrer
发明人： Kerry Bernstein , Philip G. Emma , John A. Fifield , Paul D. Kartschoke , William A. Klaasen , Norman J. Rohrer
IPC分类号： H03K19/20 , H03K19/094 , H03K19/003
CPC分类号： H03K19/007
摘要： The invention includes an error correcting logic system that allows critical circuits to be hardened with only one redundant unit and without loss of circuit performance. The system provides an interconnecting gate that suppresses a fault in one of at least two redundant dynamic logic gates that feed to the interconnecting gate. The system is applicable to dynamic or static logic systems. The system prevents propagation of a fault, and addresses not only soft errors, but noise-induced errors. Also, there is provided a design structure embodied in a machine readable medium used in a design process, and which includes such error correcting logic system.
摘要翻译： 本发明包括纠错逻辑系统，其允许仅使用一个冗余单元来硬化关键电路并且不损失电路性能。 该系统提供互连门，其抑制馈送到互连门的至少两个冗余动态逻辑门之一的故障。 该系统适用于动态或静态逻辑系统。 该系统防止故障传播，不仅解决软错误，而且还会引起噪声引起的错误。 此外，提供了在设计过程中使用的机器可读介质中体现的设计结构，并且包括这种纠错逻辑系统。
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公开(公告)号：US07336102B2
公开(公告)日：2008-02-26
申请号：US10710641
申请日：2004-07-27
申请人： Kerry Bernstein , Philip G. Emma , John A. Fifield , Paul D. Kartschoke , William A. Klaasen , Norman J. Rohrer
发明人： Kerry Bernstein , Philip G. Emma , John A. Fifield , Paul D. Kartschoke , William A. Klaasen , Norman J. Rohrer
IPC分类号： H03K19/20 , H03K19/094 , H03K19/003
CPC分类号： H03K19/007
摘要： The invention includes an error correcting logic system that allows critical circuits to be hardened with only one redundant unit and without loss of circuit performance. The system provides an interconnecting gate that suppresses a fault in one of at least two redundant dynamic logic gates that feed to the interconnecting gate. The system is applicable to dynamic or static logic systems. The system prevents propagation of a fault, and addresses not only soft errors, but noise-induced errors.
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公开(公告)号：US20090002015A1
公开(公告)日：2009-01-01
申请号：US11850857
申请日：2007-09-06
申请人： Kerry Bernstein , Philip G. Emma , John A. Fifield , Paul D. Kartschoke , William A. Klaasen , Norman J. Rohrer
发明人： Kerry Bernstein , Philip G. Emma , John A. Fifield , Paul D. Kartschoke , William A. Klaasen , Norman J. Rohrer
IPC分类号： H03K19/003
CPC分类号： H03K19/007
摘要： The invention includes an error correcting logic system that allows critical circuits to be hardened with only one redundant unit and without loss of circuit performance. The system provides an interconnecting gate that suppresses a fault in one of at least two redundant dynamic logic gates that feed to the interconnecting gate. The system is applicable to dynamic or static logic systems. The system prevents propagation of a fault, and addresses not only soft errors, but noise-induced errors. Also, there is provided a design structure embodied in a machine readable medium used in a design process, and which includes such error correcting logic system.
摘要翻译： 本发明包括纠错逻辑系统，其允许仅使用一个冗余单元来硬化关键电路并且不损失电路性能。 该系统提供互连门，其抑制馈送到互连门的至少两个冗余动态逻辑门之一的故障。 该系统适用于动态或静态逻辑系统。 该系统防止故障传播，不仅解决软错误，而且还会引起噪声引起的错误。 此外，提供了在设计过程中使用的机器可读介质中体现的设计结构，并且包括这种纠错逻辑系统。
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公开(公告)号：US07471115B2
公开(公告)日：2008-12-30
申请号：US11926386
申请日：2007-10-29
申请人： Kerry Bernstein , Philip G. Emma , John A. Fifield , Paul D. Kartschoke , William A. Klaasen , Norman J. Rohrer
发明人： Kerry Bernstein , Philip G. Emma , John A. Fifield , Paul D. Kartschoke , William A. Klaasen , Norman J. Rohrer
IPC分类号： H03K19/096 , H03K19/094
CPC分类号： H03K19/007
摘要： The invention includes an error correcting logic system that allows critical circuits to be hardened with only one redundant unit and without loss of circuit performance. The system provides an interconnecting gate that suppresses a fault in one of at least two redundant dynamic logic gates that feed to the interconnecting gate. The system is applicable to dynamic or static logic systems. The system prevents propagation of a fault, and addresses not only soft errors, but noise-induced errors.
摘要翻译： 本发明包括纠错逻辑系统，其允许仅使用一个冗余单元来硬化关键电路并且不损失电路性能。 该系统提供互连门，其抑制馈送到互连门的至少两个冗余动态逻辑门之一的故障。 该系统适用于动态或静态逻辑系统。 该系统防止故障传播，不仅解决软错误，而且还会引起噪声引起的错误。
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公开(公告)号：US06794901B2
公开(公告)日：2004-09-21
申请号：US10064921
申请日：2002-08-29
申请人： Kerry Bernstein , Philip G. Emma , John A. Fifield , Paul D. Kartschoke , Norman J. Rohrer , Peter A. Sandon
发明人： Kerry Bernstein , Philip G. Emma , John A. Fifield , Paul D. Kartschoke , Norman J. Rohrer , Peter A. Sandon
IPC分类号： H03K19096
CPC分类号： H03K19/0963 , H03K19/00338
摘要： An integrated circuit that includes a dynamic logic gate having an output node at which a logical output value of the logic gate is detected and also includes a circuit for selectable alteration of the soft error susceptibility of the dynamic logic gate.
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7.发明授权公开(公告)号：US08729549B2
公开(公告)日：2014-05-20
申请号：US13533191
申请日：2012-06-26
申请人： Kerry Bernstein , Jerome L. Cann , Christopher M. Durham , Paul D. Kartschoke , Peter J. Klim , Donald L. Wheater
发明人： Kerry Bernstein , Jerome L. Cann , Christopher M. Durham , Paul D. Kartschoke , Peter J. Klim , Donald L. Wheater
IPC分类号： H01L23/58
CPC分类号： H01L22/32 , H01L21/4846 , H01L21/6835 , H01L21/76898 , H01L23/49827 , H01L24/11 , H01L24/13 , H01L25/0657 , H01L25/50 , H01L2221/6835 , H01L2224/13005 , H01L2224/16 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06596 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079
摘要： A plurality of peripheral test structure substrate (PTSS) through vias is formed within a peripheral test structure substrate. A peripheral test structure layer and at least one functional layer are formed on one side of the plurality of the PTSS through vias. The other side of the plurality of the PTSS through vias is exposed throughout fabrication of the peripheral test structure layer and the at least one functional layer to provide access points for testing functionality of the various layers throughout the manufacturing sequence. C4 bonding may be performed after manufacture of all of the at least one functional layer is completed. A 3D assembly carrier or a C4 carrier substrate is not required since the peripheral test structure substrate has sufficient mechanical strength to support the peripheral test structure layer and the at least one functional layer.
摘要翻译： 在外围测试结构衬底内形成通孔的多个外围测试结构衬底（PTSS）。 周边测试结构层和至少一个功能层通过通孔形成在多个PTSS的一侧上。 多个PTSS通孔中的另一侧在外围测试结构层和至少一个功能层的制造过程中暴露出来，以提供用于在整个制造顺序中测试各个层的功能性的接入点。 可以在完成所有至少一个功能层的所有制造之后执行C4键合。 不需要3D组装载体或C4载体衬底，因为外围测试结构衬底具有足够的机械强度以支撑外围测试结构层和至少一个功能层。
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公开(公告)号：US20120262197A1
公开(公告)日：2012-10-18
申请号：US13533191
申请日：2012-06-26
申请人： Kerry Bernstein , Jerome L. Cann , Christopher M. Durham , Paul D. Kartschoke , Peter J. Klim , Donald L. Wheater
发明人： Kerry Bernstein , Jerome L. Cann , Christopher M. Durham , Paul D. Kartschoke , Peter J. Klim , Donald L. Wheater
IPC分类号： G01R31/3187 , G01R1/067 , G01R31/00 , G01R31/02
CPC分类号： H01L22/32 , H01L21/4846 , H01L21/6835 , H01L21/76898 , H01L23/49827 , H01L24/11 , H01L24/13 , H01L25/0657 , H01L25/50 , H01L2221/6835 , H01L2224/13005 , H01L2224/16 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06596 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079
摘要： A plurality of peripheral test structure substrate (PTSS) through vias is formed within a peripheral test structure substrate. A peripheral test structure layer and at least one functional layer are formed on one side of the plurality of the PTSS through vias. The other side of the plurality of the PTSS through vias is exposed throughout fabrication of the peripheral test structure layer and the at least one functional layer to provide access points for testing functionality of the various layers throughout the manufacturing sequence. C4 bonding may be performed after manufacture of all of the at least one functional layer is completed. A 3D assembly carrier or a C4 carrier substrate is not required since the peripheral test structure substrate has sufficient mechanical strength to support the peripheral test structure layer and the at least one functional layer.
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9.发明申请公开(公告)号：US20120264241A1
公开(公告)日：2012-10-18
申请号：US13533188
申请日：2012-06-26
申请人： Kerry Bernstein , Jerome L. Cann , Christopher M. Durham , Paul D. Kartschoke , Peter J. Klim , Donald L. Wheater
发明人： Kerry Bernstein , Jerome L. Cann , Christopher M. Durham , Paul D. Kartschoke , Peter J. Klim , Donald L. Wheater
IPC分类号： H01L21/66
CPC分类号： H01L22/32 , H01L21/4846 , H01L21/6835 , H01L21/76898 , H01L23/49827 , H01L24/11 , H01L24/13 , H01L25/0657 , H01L25/50 , H01L2221/6835 , H01L2224/13005 , H01L2224/16 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06596 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079
摘要： A plurality of peripheral test structure substrate (PTSS) through vias is formed within a peripheral test structure substrate. A peripheral test structure layer and at least one functional layer are formed on one side of the plurality of the PTSS through vias. The other side of the plurality of the PTSS through vias is exposed throughout fabrication of the peripheral test structure layer and the at least one functional layer to provide access points for testing functionality of the various layers throughout the manufacturing sequence. C4 bonding may be performed after manufacture of all of the at least one functional layer is completed. A 3D assembly carrier or a C4 carrier substrate is not required since the peripheral test structure substrate has sufficient mechanical strength to support the peripheral test structure layer and the at least one functional layer.
摘要翻译： 在外围测试结构衬底内形成通孔的多个外围测试结构衬底（PTSS）。 周边测试结构层和至少一个功能层通过通孔形成在多个PTSS的一侧上。 多个PTSS通孔中的另一侧在外围测试结构层和至少一个功能层的制造过程中暴露出来，以提供用于在整个制造顺序中测试各个层的功能性的接入点。 可以在完成所有至少一个功能层的所有制造之后执行C4键合。 不需要3D组装载体或C4载体衬底，因为外围测试结构衬底具有足够的机械强度以支撑外围测试结构层和至少一个功能层。
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10.发明申请公开(公告)号：US20090114913A1
公开(公告)日：2009-05-07
申请号：US11935724
申请日：2007-11-06
申请人： Kerry Bernstein , Jerome L. Cann , Christopher M. Durham , Paul D. Kartschoke , Peter J. Klim , Donald L. Wheater
发明人： Kerry Bernstein , Jerome L. Cann , Christopher M. Durham , Paul D. Kartschoke , Peter J. Klim , Donald L. Wheater
CPC分类号： H01L22/32 , H01L21/4846 , H01L21/6835 , H01L21/76898 , H01L23/49827 , H01L24/11 , H01L24/13 , H01L25/0657 , H01L25/50 , H01L2221/6835 , H01L2224/13005 , H01L2224/16 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06596 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079
摘要： A plurality of peripheral test structure substrate (PTSS) through vias is formed within a peripheral test structure substrate. A peripheral test structure layer and at least one functional layer are formed on one side of the plurality of the PTSS through vias. The other side of the plurality of the PTSS through vias is exposed throughout fabrication of the peripheral test structure layer and the at least one functional layer to provide access points for testing functionality of the various layers throughout the manufacturing sequence. C4 bonding may be performed after manufacture of all of the at least one functional layer is completed. A 3D assembly carrier or a C4 carrier substrate is not required since the peripheral test structure substrate has sufficient mechanical strength to support the peripheral test structure layer and the at least one functional layer.
摘要翻译： 在外围测试结构衬底内形成通孔的多个外围测试结构衬底（PTSS）。 周边测试结构层和至少一个功能层通过通孔形成在多个PTSS的一侧上。 多个PTSS通孔中的另一侧在外围测试结构层和至少一个功能层的制造过程中暴露出来，以提供用于在整个制造顺序中测试各个层的功能性的接入点。 可以在完成所有至少一个功能层的所有制造之后执行C4键合。 不需要3D组装载体或C4载体衬底，因为外围测试结构衬底具有足够的机械强度以支撑外围测试结构层和至少一个功能层。
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