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    Methodology for fixing Qcrit at design timing impact
    1.
    发明授权
    Methodology for fixing Qcrit at design timing impact 失效
    在设计时间上影响Qcrit的方法

    公开(公告)号：US06954916B2

    公开(公告)日：2005-10-11

    申请号：US10604179

    申请日：2003-06-30

    申请人： Kerry Bernstein ,  Philip G. Emma ,  Leendert M. Huisman ,  Paul D. Kartschoke ,  Norman J. Rohrer

    发明人： Kerry Bernstein ,  Philip G. Emma ,  Leendert M. Huisman ,  Paul D. Kartschoke ,  Norman J. Rohrer

    IPC分类号： G06F9/45 ,  G06F17/50

    CPC分类号： G06F17/5022

    摘要： A method and system for simulating an integrated circuit. The method includes the steps of performing a timing analysis of the circuits to ensure that they meet specified timing criteria, performing soft error analysis of the circuits to determine whether they meet specified soft error criteria, and improving those circuits that fail the soft error analysis to improve their resistance to soft errors and having no degradation on timing. Preferably, the improving step includes the step of improving those circuits that fail the soft error analysis by either having an additional voltage source or altering the capacitance of the circuits.

    摘要翻译： 一种用于模拟集成电路的方法和系统。 该方法包括以下步骤：执行电路的定时分析，以确保它们满足规定的时序准则，执行电路的软错误分析，以确定它们是否符合指定的软错误标准，以及改进那些无法通过软错误分析的电路 提高其对软错误的抵抗力，并且在时序上没有劣化。 优选地，改进步骤包括通过具有附加电压源或改变电路的电容来改进不能通过软误差分析的那些电路的步骤。

    Error correcting logic system
    2.
    发明授权
    Error correcting logic system 有权
    错误校正逻辑系统

    公开(公告)号：US07642813B2

    公开(公告)日：2010-01-05

    申请号：US11850857

    申请日：2007-09-06

    申请人： Kerry Bernstein ,  Philip G. Emma ,  John A. Fifield ,  Paul D. Kartschoke ,  William A. Klaasen ,  Norman J. Rohrer

    发明人： Kerry Bernstein ,  Philip G. Emma ,  John A. Fifield ,  Paul D. Kartschoke ,  William A. Klaasen ,  Norman J. Rohrer

    IPC分类号： H03K19/20 ,  H03K19/094 ,  H03K19/003

    CPC分类号： H03K19/007

    摘要： The invention includes an error correcting logic system that allows critical circuits to be hardened with only one redundant unit and without loss of circuit performance. The system provides an interconnecting gate that suppresses a fault in one of at least two redundant dynamic logic gates that feed to the interconnecting gate. The system is applicable to dynamic or static logic systems. The system prevents propagation of a fault, and addresses not only soft errors, but noise-induced errors. Also, there is provided a design structure embodied in a machine readable medium used in a design process, and which includes such error correcting logic system.

    摘要翻译： 本发明包括纠错逻辑系统，其允许仅使用一个冗余单元来硬化关键电路并且不损失电路性能。 该系统提供互连门，其抑制馈送到互连门的至少两个冗余动态逻辑门之一的故障。 该系统适用于动态或静态逻辑系统。 该系统防止故障传播，不仅解决软错误，而且还会引起噪声引起的错误。 此外，提供了在设计过程中使用的机器可读介质中体现的设计结构，并且包括这种纠错逻辑系统。

    ERROR CORRECTING LOGIC SYSTEM
    4.
    发明申请
    ERROR CORRECTING LOGIC SYSTEM 有权
    错误修正逻辑系统

    公开(公告)号：US20090002015A1

    公开(公告)日：2009-01-01

    申请号：US11850857

    申请日：2007-09-06

    申请人： Kerry Bernstein ,  Philip G. Emma ,  John A. Fifield ,  Paul D. Kartschoke ,  William A. Klaasen ,  Norman J. Rohrer

    发明人： Kerry Bernstein ,  Philip G. Emma ,  John A. Fifield ,  Paul D. Kartschoke ,  William A. Klaasen ,  Norman J. Rohrer

    IPC分类号： H03K19/003

    CPC分类号： H03K19/007

    摘要： The invention includes an error correcting logic system that allows critical circuits to be hardened with only one redundant unit and without loss of circuit performance. The system provides an interconnecting gate that suppresses a fault in one of at least two redundant dynamic logic gates that feed to the interconnecting gate. The system is applicable to dynamic or static logic systems. The system prevents propagation of a fault, and addresses not only soft errors, but noise-induced errors. Also, there is provided a design structure embodied in a machine readable medium used in a design process, and which includes such error correcting logic system.

    摘要翻译： 本发明包括纠错逻辑系统，其允许仅使用一个冗余单元来硬化关键电路并且不损失电路性能。 该系统提供互连门，其抑制馈送到互连门的至少两个冗余动态逻辑门之一的故障。 该系统适用于动态或静态逻辑系统。 该系统防止故障传播，不仅解决软错误，而且还会引起噪声引起的错误。 此外，提供了在设计过程中使用的机器可读介质中体现的设计结构，并且包括这种纠错逻辑系统。

    Error correcting logic system
    5.
    发明授权
    Error correcting logic system 有权
    错误校正逻辑系统

    公开(公告)号：US07471115B2

    公开(公告)日：2008-12-30

    申请号：US11926386

    申请日：2007-10-29

    申请人： Kerry Bernstein ,  Philip G. Emma ,  John A. Fifield ,  Paul D. Kartschoke ,  William A. Klaasen ,  Norman J. Rohrer

    发明人： Kerry Bernstein ,  Philip G. Emma ,  John A. Fifield ,  Paul D. Kartschoke ,  William A. Klaasen ,  Norman J. Rohrer

    IPC分类号： H03K19/096 ,  H03K19/094

    CPC分类号： H03K19/007

    摘要： The invention includes an error correcting logic system that allows critical circuits to be hardened with only one redundant unit and without loss of circuit performance. The system provides an interconnecting gate that suppresses a fault in one of at least two redundant dynamic logic gates that feed to the interconnecting gate. The system is applicable to dynamic or static logic systems. The system prevents propagation of a fault, and addresses not only soft errors, but noise-induced errors.

    摘要翻译： 本发明包括纠错逻辑系统，其允许仅使用一个冗余单元来硬化关键电路并且不损失电路性能。 该系统提供互连门，其抑制馈送到互连门的至少两个冗余动态逻辑门之一的故障。 该系统适用于动态或静态逻辑系统。 该系统防止故障传播，不仅解决软错误，而且还会引起噪声引起的错误。

    SEMICONDUCTOR CHIP STACKING FOR REDUNDANCY AND YIELD IMPROVEMENT
    7.
    发明申请
    SEMICONDUCTOR CHIP STACKING FOR REDUNDANCY AND YIELD IMPROVEMENT 有权
    用于冗余和改进的半导体芯片堆叠

    公开(公告)号：US20120326333A1

    公开(公告)日：2012-12-27

    申请号：US13607680

    申请日：2012-09-08

    申请人： Kerry Bernstein ,  Philip G. Emma ,  Michael Ignatowski

    发明人： Kerry Bernstein ,  Philip G. Emma ,  Michael Ignatowski

    IPC分类号： H01L25/00

    CPC分类号： H01L25/0657 ,  H01L25/0652 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A stacked semiconductor chip comprising multiple unit chips contains multiple instances of a first chip component that have a low yield and are distributed among the multiple unit chips. An instance of the first chip component within a first unit chip is logically paired with at least another instance of the first chip component within at least another unit chip so that the combination of the multiple instances of the first chip component across the multiple unit chips constitute a functional block providing the functionality of a fully functional instance of the first chip component. The stacked semiconductor chip may include multiple instances of a second chip component having a high yield and distributed across the multiple unit chips. Multiple low yield components constitute a functional block providing an enhanced overall yield, while high yield components are utilized to their full potential functionality.

    摘要翻译： 包括多个单元芯片的堆叠半导体芯片包含具有低产出并分布在多个单元芯片之间的第一芯片组件的多个实例。 第一单元芯片内的第一芯片组件的实例与至少另一个单元芯片内的第一芯片组件的至少另一个实例进行逻辑配对，使得跨多个单元芯片的第一芯片组件的多个实例的组合构成 提供第一芯片组件的完全功能实例的功能的功能块。 层叠的半导体芯片可以包括具有高产量并分布在多个单元芯片上的第二芯片组件的多个实例。 多个低产量组分构成提供增强的总收率的功能块，而高产量组分被用于其全部潜在功能。

    3-dimensional integrated circuit architecture, structure and method for fabrication thereof
    8.
    发明授权
    3-dimensional integrated circuit architecture, structure and method for fabrication thereof 有权
    三维集成电路体系结构及其制造方法

    公开(公告)号：US07692944B2

    公开(公告)日：2010-04-06

    申请号：US12127086

    申请日：2008-05-27

    申请人： Kerry Bernstein ,  Paul W. Coteus ,  Philip G. Emma

    发明人： Kerry Bernstein ,  Paul W. Coteus ,  Philip G. Emma

    IPC分类号： G11C5/02

    CPC分类号： H01L27/0688 ,  H01L21/6835 ,  H01L21/8221 ,  H01L27/105 ,  H01L27/1052 ,  H01L2221/68359 ,  H01L2225/06541 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105

    摘要： An integrated circuit design, structure and method for fabrication thereof includes at least one logic device layer and at least two additional separate memory array layers. Each of the logic device layer and the at least two memory array layers is independently optimized for a particular type of logic device or memory device disposed therein. Preferably also disposed within the logic device layer are array sense amplifiers, memory array output drivers and like higher performance circuitry otherwise generally disposed within memory array layer substrates. All layers may be independently powered to provide additional performance enhancement.

    摘要翻译： 其制造的集成电路设计，结构和方法包括至少一个逻辑器件层和至少两个额外的分开的存储器阵列层。 对于设置在其中的特定类型的逻辑设备或存储器件，逻辑器件层和至少两个存储器阵列层中的每一个被独立地优化。 优选地还设置在逻辑器件层内的是阵列读出放大器，存储器阵列输出驱动器和类似的高性能电路，否则通常设置在存储器阵列层衬底内。 所有层可以独立供电以提供额外的性能增强。

    3-dimensional integrated circuit architecture, structure and method for fabrication thereof
    9.
    发明授权
    3-dimensional integrated circuit architecture, structure and method for fabrication thereof 有权
    三维集成电路体系结构及其制造方法

    公开(公告)号：US07408798B2

    公开(公告)日：2008-08-05

    申请号：US11278189

    申请日：2006-03-31

    申请人： Kerry Bernstein ,  Paul W. Coteus ,  Philip G. Emma

    发明人： Kerry Bernstein ,  Paul W. Coteus ,  Philip G. Emma

    IPC分类号： G11C5/02

    CPC分类号： H01L27/0688 ,  H01L21/6835 ,  H01L21/8221 ,  H01L27/105 ,  H01L27/1052 ,  H01L2221/68359 ,  H01L2225/06541 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105

    摘要： An integrated circuit design, structure and method for fabrication Thereof includes at least one logic device layer and at least two additional separate memory array layers. Each of the logic device layer and the at least two memory array layers is independently optimized for a particular type of logic device or memory device disposed therein. Preferably also disposed within the logic device layer are array sense amplifiers, memory array output drivers and like higher performance circuitry otherwise generally disposed within memory array layer substrates. All layers may be independently powered to provide additional performance enhancement.

    摘要翻译： 其制造的集成电路设计，结构和方法包括至少一个逻辑器件层和至少两个附加的独立存储器阵列层。 对于设置在其中的特定类型的逻辑设备或存储器件，逻辑器件层和至少两个存储器阵列层中的每一个被独立地优化。 优选地还设置在逻辑器件层内的是阵列读出放大器，存储器阵列输出驱动器和类似的高性能电路，否则通常设置在存储器阵列层衬底内。 所有层可以独立供电以提供额外的性能增强。

    Semiconductor chip stacking for redundancy and yield improvement
    10.
    发明授权
    Semiconductor chip stacking for redundancy and yield improvement 有权
    半导体芯片堆叠冗余和产量提高

    公开(公告)号：US08686559B2

    公开(公告)日：2014-04-01

    申请号：US13607680

    申请日：2012-09-08

    申请人： Kerry Bernstein ,  Philip G. Emma ,  Michael Ignatowski

    发明人： Kerry Bernstein ,  Philip G. Emma ,  Michael Ignatowski

    IPC分类号： H01L23/34

    CPC分类号： H01L25/0657 ,  H01L25/0652 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A stacked semiconductor chip comprising multiple unit chips contains multiple instances of a first chip component that have a low yield and are distributed among the multiple unit chips. An instance of the first chip component within a first unit chip is logically paired with at least another instance of the first chip component within at least another unit chip so that the combination of the multiple instances of the first chip component across the multiple unit chips constitute a functional block providing the functionality of a fully functional instance of the first chip component. The stacked semiconductor chip may include multiple instances of a second chip component having a high yield and distributed across the multiple unit chips. Multiple low yield components constitute a functional block providing an enhanced overall yield, while high yield components are utilized to their full potential functionality.

    摘要翻译： 包括多个单元芯片的堆叠半导体芯片包含具有低产出并分布在多个单元芯片之间的第一芯片组件的多个实例。 第一单元芯片内的第一芯片组件的实例与至少另一个单元芯片内的第一芯片组件的至少另一个实例进行逻辑配对，使得跨多个单元芯片的第一芯片组件的多个实例的组合构成 提供第一芯片组件的完全功能实例的功能的功能块。 层叠的半导体芯片可以包括具有高产量并分布在多个单元芯片上的第二芯片组件的多个实例。 多个低产量组分构成提供增强的总收率的功能块，而高产量组分被用于其全部潜在功能。