Lithography mask and methods for producing a lithography mask
    2.
    发明申请
    Lithography mask and methods for producing a lithography mask 审中-公开
    平版印刷掩模和用于制造光刻掩模的方法

    公开(公告)号:US20060210887A1

    公开(公告)日:2006-09-21

    申请号:US11366027

    申请日:2006-03-02

    IPC分类号: G03C5/00 G03F1/00

    CPC分类号: G03F1/29 G03F1/32 G03F1/38

    摘要: Lithography mask for the lithographic patterning of a resist layer on a substrate having first regions, in which the lithography mask has a nontransparent layer, and second and third regions, which differ in terms of the optical thickness of the lithography mask and in which the lithography mask is at least semitransparent. The lithography mask comprises a first section having a plurality of second regions and a plurality of third regions, which are arranged alternately and surrounded by a first region, for the lithographic production of resist openings at distances which are less than a predetermined limit distance. Furthermore, the lithography mask comprises a second section having a multiplicity of third regions, each of which is surrounded by a second region surrounded by a multiply contiguous first region, for the lithographic production of resist openings at distances which are greater than a predetermined limit distance.

    摘要翻译: 在具有第一区域的光刻掩模具有不透明层的衬底上的抗蚀剂层的光刻图案的平版印刷掩模以及在光刻掩模的光学厚度方面不同的第二和第三区域,其中光刻 面具至少是半透明的。 所述光刻掩模包括具有多个第二区域和多个第三区域的第一区段,所述第二区域和多个第三区域交替布置并被第一区域包围,用于在小于预定极限距离的距离处的抗蚀剂开口的平版印刷产生。 此外,光刻掩模包括具有多个第三区域的第二部分,每个第三区域被由多个邻接的第一区域围绕的第二区域围绕,用于在大于预定极限距离的距离处的抗蚀剂开口的平版印刷产生 。

    Method for transferring a layout of an integrated circuit level to a semiconductor substrate
    3.
    发明申请
    Method for transferring a layout of an integrated circuit level to a semiconductor substrate 审中-公开
    用于将集成电路电平的布局传送到半导体衬底的方法

    公开(公告)号:US20050196689A1

    公开(公告)日:2005-09-08

    申请号:US11071571

    申请日:2005-03-04

    IPC分类号: G03F1/30 G03F7/20 G03F9/00

    CPC分类号: G03F1/30

    摘要: A mask level layout has an arrangement of lines and spaces with the spaces interconnected by a further space. The spaces are alternately acted upon with a phase deviation with respect to the spaces, where a phase edge between spaces acted upon differently arises in the region of the further space. Alternatively, the connecting space within the layout may be filled with dark regions. An additional space is inserted in a second layout representing a further mask of the same mask set. The additional space enables formation of an insulating region on a semiconductor substrate at the location where formation of a continuous isolation trench is not possible due to the phase edges or dark regions within originally connecting spaces of the first mask. The first mask can be embodied as a hybrid mask with structures according to the principle of alternating phase masks with a large process window.

    摘要翻译: 掩模级别布局具有线和空间的布置,空间通过另外的空间互连。 空间交替地以相对于空间的相位偏移地起作用,其中空间之间的相位在另外空间的区域中不同地起作用。 或者,布局中的连接空间可以用黑色区域填充。 在另一个布局中插入一个额外的空间,表示相同掩模集的另一掩码。 附加空间使得能够在由于第一掩模的原始连接空间内的相位边缘或暗区域而不可能形成连续隔离沟槽的位置处在半导体衬底上形成绝缘区域。 第一个掩模可以实现为具有根据具有大工艺窗口的交替相位掩模原理的结构的混合掩模。

    METHOD FOR PRODUCING A STRUCTURE ON THE SURFACE OF A SUBSTRATE
    4.
    发明申请
    METHOD FOR PRODUCING A STRUCTURE ON THE SURFACE OF A SUBSTRATE 有权
    生产基材表面结构的方法

    公开(公告)号:US20080206681A1

    公开(公告)日:2008-08-28

    申请号:US12114948

    申请日:2008-05-05

    IPC分类号: G03F7/20 H01B13/00

    摘要: The present invention relates to a method for producing a structure serving as an etching mask on the surface of a substrate. In this case, a first method involves forming a first partial structure on the surface of the substrate, which has structure elements that are arranged regularly and are spaced apart essentially identically. A second method involves forming spacers on the surface of the substrate, which adjoin sidewalls of the structure elements of the first partial structure, cutouts being provided between the spacers. A third method step involves introducing filling material into the cutouts between the spacers, a surface of the spacers being uncovered. A fourth method step involves removing the spacers in order to form a second partial structure having the filling material and having structure elements that are arranged regularly and are spaced apart essentially identically. The structure to be produced is composed of the first partial structure and the second partial structure.

    摘要翻译: 本发明涉及一种在基板表面上制造用作蚀刻掩模的结构的方法。 在这种情况下,第一种方法包括在衬底的表面上形成第一部分结构,其具有规则地排列并且基本相同地间隔开的结构元件。 第二种方法包括在衬底的表面上形成间隔物,其邻接第一部分结构的结构元件的侧壁,在间隔物之间​​提供切口。 第三种方法步骤包括将填充材料引入间隔件之间的切口中,间隔件的表面未被覆盖。 第四种方法步骤包括去除间隔物,以便形成具有填充材料的第二部分结构,并具有规则排列的结构元件并且基本相同地间隔开。 要制造的结构由第一部分结构和第二部分结构组成。

    Method for optimizing the geometry of structural elements of a circuit design pattern and method for producing a photomask
    5.
    发明申请
    Method for optimizing the geometry of structural elements of a circuit design pattern and method for producing a photomask 审中-公开
    用于优化电路设计图案的结构元件的几何形状的方法和用于制造光掩模的方法

    公开(公告)号:US20060190850A1

    公开(公告)日:2006-08-24

    申请号:US11348549

    申请日:2006-02-07

    IPC分类号: G06F17/50

    CPC分类号: G03F1/36

    摘要: A method for optimizing the geometry of structural elements of a circuit pattern involves providing an overall circuit pattern of the circuit design and a plurality of basic patterns. Subsequently, the circuit pattern of the circuit design is iteratively decomposed into corresponding basic patterns in order to classify those parts of the circuit pattern of the plurality of structural elements wherein there exists a match with the basic pattern. Subsequently, further basic patterns are determined for those parts of the circuit pattern which were not previously classified. After applying a specification for optimizing the geometry of the structural elements, the optimized basic patterns are inserted into the circuit design thus achieving an improvement of the optical imaging properties.

    摘要翻译: 用于优化电路图案的结构元件的几何形状的方法包括提供电路设计和多个基本图案的总体电路图案。 随后,将电路设计的电路图案迭代地分解为对应的基本图案,以便对存在与基本图案相匹配的多个结构元件的电路图案的那些部分进行分类。 随后,对于以前未分类的电路图形的那些部分,确定了另外的基本模式。 在应用用于优化结构元件的几何形状的规范之后,将优化的基本图案插入到电路设计中,从而实现光学成像特性的改进。

    PEM fuel cell
    6.
    发明授权
    PEM fuel cell 失效
    PEM燃料电池

    公开(公告)号:US6010798A

    公开(公告)日:2000-01-04

    申请号:US894759

    申请日:1997-08-27

    摘要: A fuel cell with a proton-conducting membrane, on which catalyst material and a collector are arranged on both sides, is characterized by the following features: on the side facing the membrane (14), the collectors (16,18) are provided with an electrically conductive gas-permeable carbon aerogel with a surface roughness of

    摘要翻译: PCT No.PCT / DE96 / 00497 Sec。 371日期1997年8月27日第 102(e)日期1997年8月27日PCT提交1996年3月22日PCT公布。 公开号WO96 / 31913 日期:1996年10月10日具有质子传导膜的燃料电池在其两侧布置有催化剂材料和集电体,其特征在于:在面向膜(14)的一侧,集电体(16, 18)具有表面粗糙度<2μm的导电气体可渗透性碳气凝胶; 通过材料粘合将铂或铂合金的催化剂层(15,17)分别施加到碳气凝胶上; 并且通过等离子体化学方法沉积的具有3至50μm的层厚度的膜(14)位于催化剂层(15,17)之间。

    Exposure system and method for operating an exposure system
    7.
    发明申请
    Exposure system and method for operating an exposure system 审中-公开
    曝光系统和操作曝光系统的方法

    公开(公告)号:US20070075276A1

    公开(公告)日:2007-04-05

    申请号:US11521609

    申请日:2006-09-15

    IPC分类号: G01J3/10

    CPC分类号: G03F7/70916

    摘要: An exposure system includes a container in which a radiation source is arranged which emits electromagnetic radiation. Furthermore, an electromagnetic trap, suitable for collecting neutral particles, is arranged inside the container. An ionization unit ionizes the neutral particles emitted during the operation of the radiation source. The electromagnetic trap collects the charged particles. Thereby, the neutral particles are removed which would otherwise impair the lithographic projection by absorption or deposition on components of the exposure system. A method is disclosed for operation of an exposure system.

    摘要翻译: 曝光系统包括其中布置有发射电磁辐射的辐射源的容器。 此外,容器内设有适合收集中性粒子的电磁阱。 电离单元电离辐射源操作期间发射的中性粒子。 电磁捕集器收集带电粒子。 因此,去除中性粒子,否则会通过吸收或沉积在曝光系统的部件上来影响光刻投影。 公开了用于曝光系统的操作的方法。

    Masks for lithographic imagings and methods for fabricating the same
    8.
    发明申请
    Masks for lithographic imagings and methods for fabricating the same 失效
    用于光刻成像的掩模及其制造方法

    公开(公告)号:US20050238966A1

    公开(公告)日:2005-10-27

    申请号:US11106719

    申请日:2005-04-15

    IPC分类号: G03C5/00 G03F1/00 G03F9/00

    CPC分类号: G03F1/34 G03F1/32

    摘要: Masks having various types of structures, such as CPL, HTPSM, or CoG structures, are without positional error with respect to one another by defining positions of the structures on the mask by a single mask lithography step. A patterned absorber layer forms in a first region, the opaque and transparent sections of the CoG structures and, in a second region, the CPL structures by serving as a hard mask for the etching of the CPL structures for example, as trenches in the mask substrate.

    摘要翻译: 具有各种类型结构的掩模,例如CPL,HTPSM或CoG结构,通过通过单个掩模光刻步骤在掩模上限定结构的位置而相对于彼此没有位置误差。 图案化的吸收层形成在第一区域中,CoG结构的不透明部分和透明部分,并且在第二区域中,通过作为用于蚀刻CPL结构的硬掩模来形成CPL结构,例如作为掩模中的沟槽 基质。

    Phase shift mask
    9.
    发明申请
    Phase shift mask 有权
    相移掩模

    公开(公告)号:US20050084771A1

    公开(公告)日:2005-04-21

    申请号:US10951805

    申请日:2004-09-29

    CPC分类号: G03F1/34 G03F1/32 G03F1/36

    摘要: Semitransparent and trenchlike, absorber-free structure elements are formed jointly on a photomask formed using phase mask technology. The trenchlike structure elements are formed as trench or mesa structure using CPL technology. In a layout, dense, but also if appropriate semi-isolated and isolated, but relatively thin pattern portions are selected to fabricate them on the photomask using CPL technology. By contrast, isolated, wider pattern portions are formed as semitransparent structure elements using halftone phase mask technology. The respective process windows are relatively large and are adapted to one another. The joint process window is enlarged. In the area of dynamic memory chips, structures in a memory cell array can be formed using CPL technology and the support regions using halftone phase mask technology. In logic circuits, thin conductor tracks using CPL technology and wider conductor tracks using halftone phase mask technology can be fabricated.

    摘要翻译: 半透明和沟槽状,无吸收体的结构元件在使用相位掩模技术形成的光掩模上共同形成。 沟槽状结构元件使用CPL技术形成为沟槽或台面结构。 在布局中,密集的,但是如果合适的话,则选择半隔离和隔离,但相对薄的图案部分,以使用CPL技术在光掩模上制造它们。 相比之下,使用半色调相位掩模技术,隔离,更宽的图案部分形成为半透明结构元件。 各个处理窗口相对较大并且彼此适配。 联合过程窗口被放大。 在动态存储器芯片领域,可以使用CPL技术和使用半色调相位掩模技术的支持区域来形成存储单元阵列中的结构。 在逻辑电路中,可以制造使用CPL技术的薄导体轨迹和使用半色调相位掩模技术的更宽的导体迹线。

    Method for operating a high-temperature fuel cell installation, and a
high-temperature fuel cell installation
    10.
    发明授权
    Method for operating a high-temperature fuel cell installation, and a high-temperature fuel cell installation 失效
    用于操作高温燃料电池装置的方法和高温燃料电池装置

    公开(公告)号:US6162556A

    公开(公告)日:2000-12-19

    申请号:US90560

    申请日:1998-06-04

    摘要: The invention relates a method for operating a high-temperature fuel cell installation having a high-temperature fuel cell module. The method includes the step of producing a combustion gas having a combustion gas power for an electrochemical reaction in a high-temperature fuel cell module by a reformation process using a heat content from the electrochemical reaction in the high-temperature fuel cell module for reforming the combustion gas. The method includes the step of producing excess hydrogen that is not consumed during the electrochemical reaction in the high-temperature fuel cell module. There is the step of operating cells of the high-temperature fuel cell module with a cell voltage of less than about 0.7 V. Finally, there is the step of storing the excess hydrogen that was not consumed in the electrochemical reaction outside of the high-temperature fuel cell module. In this manner, one optimizes the effectiveness of the high-temperature fuel cell installation. In addition, the invention relates a high-temperature fuel cell installation.

    摘要翻译: 本发明涉及一种用于操作具有高温燃料电池模块的高温燃料电池装置的方法。 该方法包括通过使用来自高温燃料电池模块中的电化学反应的热含量的重整法在高温燃料电池组件中制备具有用于电化学反应的燃烧气体功率的燃烧气体的步骤,用于重整 燃烧气体。 该方法包括在高温燃料电池模块中产生电化学反应期间不消耗的过量氢的步骤。 存在以小于约0.7V的电池电压操作高温燃料电池模块的电池的步骤。最后,存在在高电压反应器外部的电化学反应中未消耗的过量氢的步骤, 温度燃料电池模块。 以这种方式,可以优化高温燃料电池安装的有效性。 此外,本发明涉及一种高温燃料电池装置。