公开(公告)号：US08001325B2

公开(公告)日：2011-08-16

申请号：US10754483

申请日：2004-01-09

申请人： Kevin Conley ,  Robert Chang ,  Wes G. Brewer ,  Eric Bone ,  Yoram Cedar

发明人： Kevin Conley ,  Robert Chang ,  Wes G. Brewer ,  Eric Bone ,  Yoram Cedar

IPC分类号： G06F12/00 ,  G06F13/00 ,  G06F13/28

CPC分类号： G06F3/0643 ,  G06F3/0619 ,  G06F3/0679

摘要： A removable data storage device that intelligently operates as one large data storage region or as multiple, smaller data storage regions is disclosed. The removable data storage device can be used in not only modern electronic products (using 32-bit addressing) but also legacy products (using 16-bit addressing). A host device can couple to the removable storage device to access data stored in/to the removable storage device. As an example, the removable data storage device can be a memory card.

摘要翻译： 公开了一种可移动数据存储设备，其智能地操作为一个大数据存储区域或多个较小的数据存储区域。 可移动数据存储设备不仅可以用于现代电子产品（使用32位寻址），还可以用于传统产品（使用16位寻址）。 主机设备可以耦合到可移动存储设备以访问存储在/移动存储设备中的数据。 作为示例，可移动数据存储设备可以是存储卡。

公开(公告)号：US20050154819A1

公开(公告)日：2005-07-14

申请号：US10754483

申请日：2004-01-09

申请人： Kevin Conley ,  Robert Chang ,  Wes Brewer ,  Eric Bone ,  Yoram Cedar

发明人： Kevin Conley ,  Robert Chang ,  Wes Brewer ,  Eric Bone ,  Yoram Cedar

IPC分类号： G06F3/06 ,  G06F3/08 ,  G06F12/08 ,  G06F13/10 ,  G06K19/07 ,  G11C8/20

CPC分类号： G06F3/0643 ,  G06F3/0619 ,  G06F3/0679

摘要： A removable data storage device that intelligently operates as one large data storage region or as multiple, smaller data storage regions is disclosed. The removable data storage device can be used in not only modern electronic products (using 32-bit addressing) but also legacy products (using 16-bit addressing). A host device can couple to the removable storage device to access data stored in/to the removable storage device. As an example, the removable data storage device can be a memory card.

摘要翻译： 公开了一种可移动数据存储设备，其智能地操作为一个大数据存储区域或多个较小的数据存储区域。 可移动数据存储设备不仅可以用于现代电子产品（使用32位寻址），还可以用于传统产品（使用16位寻址）。 主机设备可以耦合到可移动存储设备以访问存储在/移动存储设备中的数据。 作为示例，可移动数据存储设备可以是存储卡。

公开(公告)号：US20050146939A1

公开(公告)日：2005-07-07

申请号：US11058359

申请日：2005-02-14

申请人： Kevin Conley ,  Yoram Cedar

发明人： Kevin Conley ,  Yoram Cedar

IPC分类号： G06F5/06 ,  G06F12/00 ,  G11C7/10 ,  G11C11/34 ,  G11C16/06 ,  G11C16/10

CPC分类号： G11C16/105 ,  G11C16/10 ,  G11C16/102 ,  G11C2216/22

摘要： The present invention allows for an increase in programming parallelism in a non-volatile memory system without incurring additional data transfer latency. Data is transferred from a controller to a first memory chip and a programming operation is caused to begin. While that first memory chip is busy performing that program operation, data is transferred from the controller to a second memory chip and a programming operation is caused to begin in that chip. Data transfer can begin to the first memory chip again once it has completed its programming operation even though the second chip is still busy performing its program operation. In this manner high parallelism of programming operation is achieved without incurring the latency cost of performing the additional data transfers. Two sets of embodiments are presented, one that preserves the host data in a buffer until successful programming of that data is confirmed and one that does not require that success be achieved and that does not preserve the data thus achieving a higher rate of data programming throughput.

摘要翻译： 本发明允许在非易失性存储器系统中增加编程并行性，而不会引起额外的数据传输等待时间。 数据从控制器传送到第一存储器芯片，并且开始编程操作。 当该第一存储器芯片正在忙于执行该程序操作时，数据从控制器传送到第二存储器芯片，并且使该编程操作在该芯片中开始。 一旦完成编程操作，即使第二个芯片仍在忙于执行其程序操作，数据传输也可以再次开始到第一个存储器芯片。 以这种方式，实现编程操作的高并行性，而不会导致执行附加数据传输的延迟成本。 呈现了两组实施例，一种将缓冲器中的主机数据保留，直到该数据的成功编程被确认为止，并且不需要实现该成功，并且不保留数据从而实现更高的数据编程吞吐量 。

公开(公告)号：US20070136639A1

公开(公告)日：2007-06-14

申请号：US11285992

申请日：2005-11-22

申请人： Daniel Guterman ,  Yoram Cedar ,  Charles Schroter ,  Milton Barrocas ,  Carlos Gonzalez ,  Kevin Conley

发明人： Daniel Guterman ,  Yoram Cedar ,  Charles Schroter ,  Milton Barrocas ,  Carlos Gonzalez ,  Kevin Conley

IPC分类号： G11C29/00

CPC分类号： G06F13/1694 ,  G06F11/1068 ,  G11C7/00

摘要： A non-volatile memory device is provided with a controller and includes method that controls memory operations and to emulate the memory and communication characteristics of a legacy memory device. In this way, the memory device is compatible with a host that was originally designed to operate the legacy memory device. In particular, the controller performs the emulation to the host taking into account differences such as multibit memory, error correction requirement, memory support of overwrites, and erasable block sizes.

摘要翻译： 非易失性存储器件具有控制器，并且包括控制存储器操作并模拟传统存储器件的存储器和通信特性的方法。 以这种方式，存储器设备与最初设计用于操作传统存储设备的主机兼容。 特别地，控制器考虑到诸如多位存储器，错误校正要求，覆盖的存储器支持以及可擦除块大小之类的差异，对主机执行仿真。

公开(公告)号：US20070118713A1

公开(公告)日：2007-05-24

申请号：US11286100

申请日：2005-11-22

申请人： Daniel Guterman ,  Yoram Cedar ,  Charles Schroter ,  Milton Barrocas ,  Carlos Gonzalez ,  Kevin Conley

发明人： Daniel Guterman ,  Yoram Cedar ,  Charles Schroter ,  Milton Barrocas ,  Carlos Gonzalez ,  Kevin Conley

IPC分类号： G06F12/00

CPC分类号： G06F3/0664 ,  G06F3/0607 ,  G06F3/0661 ,  G06F3/0679 ,  G06F11/1048 ,  G06F13/385

摘要： A non-volatile memory device is provided with a controller and includes method that controls memory operations and to emulate the memory and communication characteristics of a legacy memory device. In this way, the memory device is compatible with a host that was originally designed to operate the legacy memory device. In particular, the controller performs the emulation to the host taking into account differences such as multibit memory, error correction requirement, memory support of overwrites, and erasable block sizes.

摘要翻译： 非易失性存储器件具有控制器，并且包括控制存储器操作并模拟传统存储器件的存储器和通信特性的方法。 以这种方式，存储器设备与最初设计用于操作传统存储设备的主机兼容。 特别地，控制器考虑到诸如多位存储器，错误校正要求，覆盖的存储器支持以及可擦除块大小之类的差异，对主机执行仿真。

公开(公告)号：US20070103978A1

公开(公告)日：2007-05-10

申请号：US11270410

申请日：2005-11-08

申请人： Kevin Conley ,  Yoram Cedar

发明人： Kevin Conley ,  Yoram Cedar

IPC分类号： G11C16/06

CPC分类号： G11C29/81 ,  G11C16/0483 ,  G11C16/16 ,  G11C29/808 ,  G11C29/82

摘要： In a memory array having redundant columns, a scheme allows defective cells to be individually remapped to redundant cells in a redundant column. Redundant cells in one redundant column replace defective cells in multiple non-redundant columns. Remapping is done as part of initial test and configuration. Specific hardware can be used for the scheme or firmware in the memory controller can implement the scheme.

摘要翻译： 在具有冗余列的存储器阵列中，一种方案允许故障单元被单独地重新映射到冗余列中的冗余单元。 一个冗余列中的冗余单元格可以替换多个非冗余列中的有缺陷单元。 重新映射作为初始测试和配置的一部分完成。 具体硬件可用于方案或固件在内存控制器中可实现的方案。

公开(公告)号：US20070091680A1

公开(公告)日：2007-04-26

申请号：US11611706

申请日：2006-12-15

申请人： Kevin Conley ,  Yoram Cedar

发明人： Kevin Conley ,  Yoram Cedar

IPC分类号： G11C16/04

CPC分类号： G11C16/105 ,  G11C16/10 ,  G11C16/102 ,  G11C2216/22

摘要： The present invention allows for an increase in programming parallelism in a non-volatile memory system without incurring additional data transfer latency. Data is transferred from a controller to a first memory chip and a programming operation is caused to begin. While that first memory chip is busy performing that program operation, data is transferred from the controller to a second memory chip and a programming operation is caused to begin in that chip. Data transfer can begin to the first memory chip again once it has completed its programming operation even though the second chip is still busy performing its program operation. In this manner high parallelism of programming operation is achieved without incurring the latency cost of performing the additional data transfers. Two sets of embodiments are presented, one that preserves the host data in a buffer until successful programming of that data is confirmed and one that does not require that success be achieved and that does not preserve the data thus achieving a higher rate of data programming throughput.

摘要翻译： 本发明允许在非易失性存储器系统中增加编程并行性，而不会引起额外的数据传输等待时间。 数据从控制器传送到第一存储器芯片，并且开始编程操作。 当该第一存储器芯片正在忙于执行该程序操作时，数据从控制器传送到第二存储器芯片，并且使该编程操作在该芯片中开始。 一旦完成编程操作，即使第二个芯片仍在忙于执行其程序操作，数据传输也可以再次开始到第一个存储器芯片。 以这种方式，实现编程操作的高并行性，而不会导致执行附加数据传输的延迟成本。 提出了两组实施例，一种将数据保存在缓冲器中，直到该数据的成功编程得到确认，并且不需要实现成功，并且不保留数据从而实现更高的数据编程吞吐量 。

公开(公告)号：US20060136656A1

公开(公告)日：2006-06-22

申请号：US11021200

申请日：2004-12-21

申请人： Kevin Conley ,  Yoram Cedar

发明人： Kevin Conley ,  Yoram Cedar

IPC分类号： G06F12/00

CPC分类号： G06F12/0893 ,  G06F12/0246 ,  G06F12/0804 ,  G06F2212/7203 ,  G11C16/12 ,  G11C16/3418 ,  G11C16/3427 ,  G11C2207/2245 ,  G11C2216/14

摘要： A method of programming a non-volatile memory array using an on-chip write cache is disclosed. Individual data packets received by the memory system are stored in cache memory. More than one data packet may be stored in this way and then programmed to a single page of the non-volatile array. This results in more efficient use of storage space in the non-volatile array.

摘要翻译： 公开了一种使用片上写高速缓存来编程非易失性存储器阵列的方法。 由存储器系统接收的各个数据分组存储在高速缓冲存储器中。 可以以这种方式存储多于一个数据分组，然后编程到非易失性阵列的单页。 这导致在非易失性阵列中更有效地使用存储空间。

公开(公告)号：US20080065818A1

公开(公告)日：2008-03-13

申请号：US11936440

申请日：2007-11-07

申请人： Jason Lin ,  Kevin Conley ,  Robert Chang

发明人： Jason Lin ,  Kevin Conley ,  Robert Chang

IPC分类号： G06F12/00

CPC分类号： G11C16/0416 ,  G11C16/10 ,  G11C16/105 ,  G11C2216/16

摘要： The present invention presents a non-volatile memory and method for its operation that ensures reliable mechanism for write and erase abort detection in the event of lost of power during non-volatile memory programming and erasing with minimized system performance penalty. During a multi-sector write process, an indication of a successful write in one sector is written into the overhead of the following sector at the same time as the following sector's data content is written. The last sector written will additionally have an indication of its own successful write written into its overhead. For erase, an erase abort flag in the first sector of the block can be marked after a successful erase operation.

摘要翻译： 本发明提供了一种用于其操作的非易失性存储器和方法，其确保在非易失性存储器编程和擦除期间由于在最小化的系统性能损失下的擦除而导致的写入和擦除中止检测的可靠机制。 在多扇区写入过程中，在写入下一个扇区的数据内容的同时，在一个扇区中成功写入的指示被写入下一个扇区的开销。 写入的最后一个部分将另外显示自己的成功写入写入其开销。 为了擦除，可以在成功擦除操作之后标记块的第一个扇区中的擦除中止标志。

公开(公告)号：US20050144362A1

公开(公告)日：2005-06-30

申请号：US10751096

申请日：2003-12-31

申请人： Jason Lin ,  Kevin Conley ,  Robert Chang

发明人： Jason Lin ,  Kevin Conley ,  Robert Chang

IPC分类号： G11C16/04 ,  G11C16/10 ,  G06F12/00

CPC分类号： G11C16/0416 ,  G11C16/10 ,  G11C16/105 ,  G11C2216/16

摘要： The present invention presents a non-volatile memory and method for its operation that ensures reliable mechanism for write and erase abort detection in the event of lost of power during non-volatile memory programming and erasing with minimized system performance penalty. During a multi-sector write process, an indication of a successful write in one sector is written into the overhead of the following sector at the same time as the following sector's data content is written. The last sector written will additionally have an indication of its own successful write written into its overhead. For erase, an erase abort flag in the first sector of the block can be marked after a successful erase operation.

摘要翻译： 本发明提供了一种用于其操作的非易失性存储器和方法，其确保在非易失性存储器编程和擦除期间由于在最小化的系统性能损失下的擦除而导致的写入和擦除中止检测的可靠机制。 在多扇区写入过程中，在写入下一个扇区的数据内容的同时，在一个扇区中成功写入的指示被写入下一个扇区的开销。 写入的最后一个部分将另外显示自己的成功写入写入其开销。 为了擦除，可以在成功擦除操作之后标记块的第一个扇区中的擦除中止标志。