公开(公告)号：US09755085B2

公开(公告)日：2017-09-05

申请号：US13537650

申请日：2012-06-29

申请人： Ki Hong Lee ,  Seung Ho Pyi ,  Jung Yun Chang

发明人： Ki Hong Lee ,  Seung Ho Pyi ,  Jung Yun Chang

IPC分类号： H01L27/088 ,  H01L21/8239 ,  H01L29/792 ,  H01L29/66 ,  H01L27/11582

CPC分类号： H01L27/11582 ,  H01L21/31111 ,  H01L21/32133 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L29/1037 ,  H01L29/66833 ,  H01L29/7926

摘要： A semiconductor device includes memory blocks each configured to comprise a pair of channels, each channel including a pipe channel formed in a pipe gate of the memory block and a drain-side channel and a source-side channel coupled to the pipe channel; first slits placed between the memory blocks adjacent to other memory blocks; and a second slit placed between the source-side channel and the drain-side channel of each pair of channels.

公开(公告)号：US09634152B2

公开(公告)日：2017-04-25

申请号：US13537650

申请日：2012-06-29

申请人： Ki Hong Lee ,  Seung Ho Pyi ,  Jung Yun Chang

发明人： Ki Hong Lee ,  Seung Ho Pyi ,  Jung Yun Chang

IPC分类号： H01L27/088 ,  H01L21/8239 ,  H01L29/792 ,  H01L29/66 ,  H01L27/11582

摘要： A semiconductor device includes memory blocks each configured to comprise a pair of channels, each channel including a pipe channel formed in a pipe gate of the memory block and a drain-side channel and a source-side channel coupled to the pipe channel; first slits placed between the memory blocks adjacent to other memory blocks; and a second slit placed between the source-side channel and the drain-side channel of each pair of channels.

公开(公告)号：US08853767B2

公开(公告)日：2014-10-07

申请号：US13601396

申请日：2012-08-31

申请人： Ki Hong Lee ,  Seung Ho Pyi ,  Seok Min Jeon

发明人： Ki Hong Lee ,  Seung Ho Pyi ,  Seok Min Jeon

IPC分类号： H01L29/792 ,  H01L27/115

CPC分类号： H01L27/11578 ,  H01L27/11519 ,  H01L27/11553 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1158 ,  H01L27/11582 ,  H01L27/12 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7889 ,  H01L29/7926

摘要： A semiconductor device includes a first source layer; at least one of a second source layer, the second source layer formed substantially in the first source layer; a plurality of conductive layers stacked substantially over the first source layer; channel layers that pass through the plurality of conductive layers and couple to the second source layer; and at least one of a third source layer, the third source layer formed substantially in the second source layer, wherein the third source layer passes through the second source layer and is coupled to the first source layer.

摘要翻译： 半导体器件包括第一源极层; 第二源层中的至少一个，所述第二源极层基本上形成在所述第一源极层中; 基本上层叠在所述第一源极层上的多个导电层; 沟道层，其穿过所述多个导电层并耦合到所述第二源极层; 以及第三源层中的至少一个，所述第三源极层基本上形成在所述第二源极层中，其中所述第三源极层穿过所述第二源极层并且耦合到所述第一源极层。

公开(公告)号：US20130087846A1

公开(公告)日：2013-04-11

申请号：US13598414

申请日：2012-08-29

申请人： Ki Hong Lee ,  Seung Ho Pyi ,  In Su Park

发明人： Ki Hong Lee ,  Seung Ho Pyi ,  In Su Park

IPC分类号： H01L21/20 ,  H01L29/792

CPC分类号： H01L27/11582 ,  H01L21/0217 ,  H01L21/31111 ,  H01L21/32133 ,  H01L29/4234 ,  H01L29/66666 ,  H01L29/66833

摘要： A semiconductor device includes word lines and interlayer insulating layers alternately stacked, a channel layer penetrating the word lines and the interlayer insulating layers, a tunnel insulating layer surrounding the channel layer, and first charge trap layers surrounding the tunnel insulating layer, interposed between the word lines and the tunnel insulating layer, respectively, and doped with first impurities.

公开(公告)号：US08872254B2

公开(公告)日：2014-10-28

申请号：US13598414

申请日：2012-08-29

申请人： Ki Hong Lee ,  Seung Ho Pyi ,  In Su Park

发明人： Ki Hong Lee ,  Seung Ho Pyi ,  In Su Park

IPC分类号： H01L29/792 ,  H01L27/115

CPC分类号： H01L27/11582 ,  H01L21/0217 ,  H01L21/31111 ,  H01L21/32133 ,  H01L29/4234 ,  H01L29/66666 ,  H01L29/66833

摘要： A semiconductor device includes word lines and interlayer insulating layers alternately stacked, a channel layer penetrating the word lines and the interlayer insulating layers, a tunnel insulating layer surrounding the channel layer, and first charge trap layers surrounding the tunnel insulating layer, interposed between the word lines and the tunnel insulating layer, respectively, and doped with first impurities.

摘要翻译： 半导体器件包括交替堆叠的字线和层间绝缘层，穿透字线和层间绝缘层的沟道层，围绕沟道层的隧道绝缘层和围绕隧道绝缘层的第一电荷陷阱层，插入在字 线路和隧道绝缘层，并掺杂有第一杂质。

公开(公告)号：US20130207178A1

公开(公告)日：2013-08-15

申请号：US13603339

申请日：2012-09-04

申请人： Ki Hong Lee ,  Seung Ho Pyi ,  Hyun Soo Shon

发明人： Ki Hong Lee ,  Seung Ho Pyi ,  Hyun Soo Shon

IPC分类号： H01L29/792 ,  H01L21/336

CPC分类号： H01L27/11582 ,  H01L21/28282 ,  H01L21/32133 ,  H01L29/66666 ,  H01L29/66833 ,  H01L29/7926

摘要： A semiconductor device includes word lines and interlayer insulating layers alternately stacked over a substrate, vertical channel layers protruding from the substrate and passing through the word lines and the interlayer insulating layers, a tunnel insulating layer surrounding each of the vertical channel layers, a charge trap layer surrounding the tunnel insulating layer, wherein first regions of the charge trap layer between the tunnel insulating layer and the word lines have a thickness smaller than a thickness of second regions thereof between the tunnel insulating layer and the interlayer insulating layers, and first charge blocking layer patterns surrounding the first regions of the charge trap layer.

公开(公告)号：US20090163014A1

公开(公告)日：2009-06-25

申请号：US12139623

申请日：2008-06-16

申请人： Ki Hong Lee ,  Seung Ho Pyi ,  Ki Seon Park

发明人： Ki Hong Lee ,  Seung Ho Pyi ,  Ki Seon Park

IPC分类号： H01L21/28

CPC分类号： H01L21/28282 ,  H01L21/3105 ,  H01L21/31608 ,  H01L21/31616

摘要： A method for fabricating a non-volatile memory device with a charge trapping layer wherein a tunneling layer, a charge trapping layer, a blocking layer, and a control gate electrode are formed on a semiconductor substrate. A temperature of the control gate electrode is increased by applying a magnetic field to the control gate electrode. The blocking layer is densified by allowing the increased temperature to be transferred to the blocking layer contacting the control gate electrode.

摘要翻译： 一种用于制造具有电荷捕获层的非易失性存储器件的方法，其中在半导体衬底上形成有隧道层，电荷俘获层，阻挡层和控制栅电极。 通过向控制栅电极施加磁场来增加控制栅电极的温度。 通过允许将升高的温度转移到与控制栅电极接触的阻挡层而使阻挡层致密化。

公开(公告)号：US07919371B2

公开(公告)日：2011-04-05

申请号：US12139623

申请日：2008-06-16

申请人： Ki Hong Lee ,  Seung Ho Pyi ,  Ki Seon Park

发明人： Ki Hong Lee ,  Seung Ho Pyi ,  Ki Seon Park

IPC分类号： H01L21/336

CPC分类号： H01L21/28282 ,  H01L21/3105 ,  H01L21/31608 ,  H01L21/31616

摘要： A method for fabricating a non-volatile memory device with a charge trapping layer wherein a tunneling layer, a charge trapping layer, a blocking layer, and a control gate electrode are formed on a semiconductor substrate. A temperature of the control gate electrode is increased by applying a magnetic field to the control gate electrode. The blocking layer is densified by allowing the increased temperature to be transferred to the blocking layer contacting the control gate electrode.

摘要翻译： 一种用于制造具有电荷捕获层的非易失性存储器件的方法，其中在半导体衬底上形成有隧道层，电荷俘获层，阻挡层和控制栅电极。 通过向控制栅电极施加磁场来增加控制栅电极的温度。 通过允许将升高的温度转移到与控制栅电极接触的阻挡层而使阻挡层致密化。

公开(公告)号：US08946808B2

公开(公告)日：2015-02-03

申请号：US13603339

申请日：2012-09-04

申请人： Ki Hong Lee ,  Seung Ho Pyi ,  Hyun Soo Shon

发明人： Ki Hong Lee ,  Seung Ho Pyi ,  Hyun Soo Shon

IPC分类号： H01L29/792 ,  H01L29/76 ,  H01L29/788 ,  H01L21/4763

CPC分类号： H01L27/11582 ,  H01L21/28282 ,  H01L21/32133 ,  H01L29/66666 ,  H01L29/66833 ,  H01L29/7926

摘要： A semiconductor device includes word lines and interlayer insulating layers alternately stacked over a substrate, vertical channel layers protruding from the substrate and passing through the word lines and the interlayer insulating layers, a tunnel insulating layer surrounding each of the vertical channel layers, a charge trap layer surrounding the tunnel insulating layer, wherein first regions of the charge trap layer between the tunnel insulating layer and the word lines have a thickness smaller than a thickness of second regions thereof between the tunnel insulating layer and the interlayer insulating layers, and first charge blocking layer patterns surrounding the first regions of the charge trap layer.

公开(公告)号：US08890251B2

公开(公告)日：2014-11-18

申请号：US13598604

申请日：2012-08-29

申请人： Ki Hong Lee ,  Seung Ho Pyi ,  Il Young Kwon

发明人： Ki Hong Lee ,  Seung Ho Pyi ,  Il Young Kwon

IPC分类号： H01L29/40

CPC分类号： H01L27/11582 ,  H01L21/76802 ,  H01L21/76841 ,  H01L21/76877 ,  H01L29/4238 ,  H01L29/66833 ,  H01L29/7926

摘要： A semiconductor device includes a substrate, and a gate line, located over the substrate, which includes a first conductive layer and one or more second conductive pattern layers located in the first conductive layer. The second conductive pattern layer comprises a metal layer to thus reduce resistance of a gate line.

摘要翻译： 半导体器件包括位于衬底上方的衬底和栅极线，栅极线包括第一导电层和位于第一导电层中的一个或多个第二导电图案层。 第二导电图案层包括金属层，从而降低栅极线的电阻。