公开(公告)号：US09620513B2

公开(公告)日：2017-04-11

申请号：US13599148

申请日：2012-08-30

申请人： Ki Hong Lee ,  Seung Ho Pyi ,  Sung Ik Moon

发明人： Ki Hong Lee ,  Seung Ho Pyi ,  Sung Ik Moon

IPC分类号： H01L27/11 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/11548 ,  H01L27/11575

CPC分类号： H01L27/11582 ,  H01L21/0332 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11575

摘要： A semiconductor device includes a cell structure; n first pad structures formed on one side of the cell structure and each configured to have a step form in which 2n layers form one stage; and n second pad structures formed on the other side of the cell structure each configured to have a step form in which 2n layers form one stage, wherein n is a natural number of 1 or higher, and the first pad structures and the second pad structures have asymmetrical step forms having different heights.

公开(公告)号：US09755085B2

公开(公告)日：2017-09-05

申请号：US13537650

申请日：2012-06-29

申请人： Ki Hong Lee ,  Seung Ho Pyi ,  Jung Yun Chang

发明人： Ki Hong Lee ,  Seung Ho Pyi ,  Jung Yun Chang

IPC分类号： H01L27/088 ,  H01L21/8239 ,  H01L29/792 ,  H01L29/66 ,  H01L27/11582

CPC分类号： H01L27/11582 ,  H01L21/31111 ,  H01L21/32133 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L29/1037 ,  H01L29/66833 ,  H01L29/7926

摘要： A semiconductor device includes memory blocks each configured to comprise a pair of channels, each channel including a pipe channel formed in a pipe gate of the memory block and a drain-side channel and a source-side channel coupled to the pipe channel; first slits placed between the memory blocks adjacent to other memory blocks; and a second slit placed between the source-side channel and the drain-side channel of each pair of channels.

公开(公告)号：US08853767B2

公开(公告)日：2014-10-07

申请号：US13601396

申请日：2012-08-31

申请人： Ki Hong Lee ,  Seung Ho Pyi ,  Seok Min Jeon

发明人： Ki Hong Lee ,  Seung Ho Pyi ,  Seok Min Jeon

IPC分类号： H01L29/792 ,  H01L27/115

CPC分类号： H01L27/11578 ,  H01L27/11519 ,  H01L27/11553 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1158 ,  H01L27/11582 ,  H01L27/12 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7889 ,  H01L29/7926

摘要： A semiconductor device includes a first source layer; at least one of a second source layer, the second source layer formed substantially in the first source layer; a plurality of conductive layers stacked substantially over the first source layer; channel layers that pass through the plurality of conductive layers and couple to the second source layer; and at least one of a third source layer, the third source layer formed substantially in the second source layer, wherein the third source layer passes through the second source layer and is coupled to the first source layer.

摘要翻译： 半导体器件包括第一源极层; 第二源层中的至少一个，所述第二源极层基本上形成在所述第一源极层中; 基本上层叠在所述第一源极层上的多个导电层; 沟道层，其穿过所述多个导电层并耦合到所述第二源极层; 以及第三源层中的至少一个，所述第三源极层基本上形成在所述第二源极层中，其中所述第三源极层穿过所述第二源极层并且耦合到所述第一源极层。

公开(公告)号：US20130087846A1

公开(公告)日：2013-04-11

申请号：US13598414

申请日：2012-08-29

申请人： Ki Hong Lee ,  Seung Ho Pyi ,  In Su Park

发明人： Ki Hong Lee ,  Seung Ho Pyi ,  In Su Park

IPC分类号： H01L21/20 ,  H01L29/792

CPC分类号： H01L27/11582 ,  H01L21/0217 ,  H01L21/31111 ,  H01L21/32133 ,  H01L29/4234 ,  H01L29/66666 ,  H01L29/66833

摘要： A semiconductor device includes word lines and interlayer insulating layers alternately stacked, a channel layer penetrating the word lines and the interlayer insulating layers, a tunnel insulating layer surrounding the channel layer, and first charge trap layers surrounding the tunnel insulating layer, interposed between the word lines and the tunnel insulating layer, respectively, and doped with first impurities.

公开(公告)号：US08872254B2

公开(公告)日：2014-10-28

申请号：US13598414

申请日：2012-08-29

申请人： Ki Hong Lee ,  Seung Ho Pyi ,  In Su Park

发明人： Ki Hong Lee ,  Seung Ho Pyi ,  In Su Park

IPC分类号： H01L29/792 ,  H01L27/115

CPC分类号： H01L27/11582 ,  H01L21/0217 ,  H01L21/31111 ,  H01L21/32133 ,  H01L29/4234 ,  H01L29/66666 ,  H01L29/66833

摘要： A semiconductor device includes word lines and interlayer insulating layers alternately stacked, a channel layer penetrating the word lines and the interlayer insulating layers, a tunnel insulating layer surrounding the channel layer, and first charge trap layers surrounding the tunnel insulating layer, interposed between the word lines and the tunnel insulating layer, respectively, and doped with first impurities.

摘要翻译： 半导体器件包括交替堆叠的字线和层间绝缘层，穿透字线和层间绝缘层的沟道层，围绕沟道层的隧道绝缘层和围绕隧道绝缘层的第一电荷陷阱层，插入在字 线路和隧道绝缘层，并掺杂有第一杂质。

公开(公告)号：US20130207178A1

公开(公告)日：2013-08-15

申请号：US13603339

申请日：2012-09-04

申请人： Ki Hong Lee ,  Seung Ho Pyi ,  Hyun Soo Shon

发明人： Ki Hong Lee ,  Seung Ho Pyi ,  Hyun Soo Shon

IPC分类号： H01L29/792 ,  H01L21/336

CPC分类号： H01L27/11582 ,  H01L21/28282 ,  H01L21/32133 ,  H01L29/66666 ,  H01L29/66833 ,  H01L29/7926

摘要： A semiconductor device includes word lines and interlayer insulating layers alternately stacked over a substrate, vertical channel layers protruding from the substrate and passing through the word lines and the interlayer insulating layers, a tunnel insulating layer surrounding each of the vertical channel layers, a charge trap layer surrounding the tunnel insulating layer, wherein first regions of the charge trap layer between the tunnel insulating layer and the word lines have a thickness smaller than a thickness of second regions thereof between the tunnel insulating layer and the interlayer insulating layers, and first charge blocking layer patterns surrounding the first regions of the charge trap layer.

公开(公告)号：US20090163014A1

公开(公告)日：2009-06-25

申请号：US12139623

申请日：2008-06-16

申请人： Ki Hong Lee ,  Seung Ho Pyi ,  Ki Seon Park

发明人： Ki Hong Lee ,  Seung Ho Pyi ,  Ki Seon Park

IPC分类号： H01L21/28

CPC分类号： H01L21/28282 ,  H01L21/3105 ,  H01L21/31608 ,  H01L21/31616

摘要： A method for fabricating a non-volatile memory device with a charge trapping layer wherein a tunneling layer, a charge trapping layer, a blocking layer, and a control gate electrode are formed on a semiconductor substrate. A temperature of the control gate electrode is increased by applying a magnetic field to the control gate electrode. The blocking layer is densified by allowing the increased temperature to be transferred to the blocking layer contacting the control gate electrode.

摘要翻译： 一种用于制造具有电荷捕获层的非易失性存储器件的方法，其中在半导体衬底上形成有隧道层，电荷俘获层，阻挡层和控制栅电极。 通过向控制栅电极施加磁场来增加控制栅电极的温度。 通过允许将升高的温度转移到与控制栅电极接触的阻挡层而使阻挡层致密化。

公开(公告)号：US09634152B2

公开(公告)日：2017-04-25

申请号：US13537650

申请日：2012-06-29

申请人： Ki Hong Lee ,  Seung Ho Pyi ,  Jung Yun Chang

发明人： Ki Hong Lee ,  Seung Ho Pyi ,  Jung Yun Chang

IPC分类号： H01L27/088 ,  H01L21/8239 ,  H01L29/792 ,  H01L29/66 ,  H01L27/11582

摘要： A semiconductor device includes memory blocks each configured to comprise a pair of channels, each channel including a pipe channel formed in a pipe gate of the memory block and a drain-side channel and a source-side channel coupled to the pipe channel; first slits placed between the memory blocks adjacent to other memory blocks; and a second slit placed between the source-side channel and the drain-side channel of each pair of channels.

公开(公告)号：US09099348B2

公开(公告)日：2015-08-04

申请号：US13602038

申请日：2012-08-31

申请人： Ki Hong Lee ,  Seung Ho Pyi ,  Hyun Soo Shon

发明人： Ki Hong Lee ,  Seung Ho Pyi ,  Hyun Soo Shon

IPC分类号： H01L29/76 ,  H01L27/115

CPC分类号： H01L27/11582 ,  H01L27/11573

摘要： A semiconductor device includes: vertical channel layers; a pipe channel layer configured to connect lower ends of the vertical channel layers; and a pipe gate surrounding the pipe channel layer and including a first region, which is in contact with the pipe channel layer and includes a first-type impurity, and remaining second regions including a second-type impurity different from the first type impurity.

摘要翻译： 半导体器件包括：垂直沟道层; 管道沟道层，被配置为连接垂直沟道层的下端; 以及围绕所述管道沟道层的管道浇口，并且包括与所述管道沟道层接触并且包括第一类型杂质的第一区域，以及包括与所述第一类型杂质不同的第二类型杂质的剩余的第二区域。

公开(公告)号：US08878277B2

公开(公告)日：2014-11-04

申请号：US13598528

申请日：2012-08-29

申请人： Ki Hong Lee ,  Seung Ho Pyi ,  Seok Min Jeon

发明人： Ki Hong Lee ,  Seung Ho Pyi ,  Seok Min Jeon

IPC分类号： H01L29/76

CPC分类号： H01L27/11582 ,  H01L29/66833 ,  H01L29/7926

摘要： A 3D non-volatile memory device includes a pipe gate, at least one first channel layer including a first pipe channel layer formed in the pipe gate and a pair of first source side channel layer and first drain side channel layer connected to the first pipe channel layer, and at least one second channel layer including a second pipe channel layer formed in the pipe gate and positioned over the first pipe channel layer and a pair of second source side channel layer and second drain side channel layer connected to the second pipe channel layer.

摘要翻译： 3D非易失性存储器件包括管道浇口，至少一个第一沟道层，其包括形成在管道栅极中的第一管道沟道层，以及一对第一源极侧沟道层和与第一管道沟道连接的第一漏极侧沟道层 层，以及至少一个第二沟道层，其包括形成在管道浇口中并位于第一管道沟道层上的第二管道沟道层和连接到第二管道沟道层的一对第二源极侧沟道层和第二漏极侧沟道层 。