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    Optical semiconductor device
    1.
    发明申请
    Optical semiconductor device 审中-公开
    光半导体器件

    公开(公告)号：US20060133440A1

    公开(公告)日：2006-06-22

    申请号：US11170813

    申请日：2005-06-30

    申请人： Ki Kim ,  Chul Lee ,  Dong Lee ,  Jung Song ,  Eun Sim ,  Sung Kim ,  Yong Baek

    发明人： Ki Kim ,  Chul Lee ,  Dong Lee ,  Jung Song ,  Eun Sim ,  Sung Kim ,  Yong Baek

    IPC分类号： H01S5/20

    CPC分类号： H01S5/3434 ,  B82Y20/00 ,  H01L33/06 ,  H01S5/2004 ,  H01S5/2009 ,  H01S5/3403 ,  H01S5/34373

    摘要： Provided is an optical semiconductor device including: an active layer having at least one quantum well layer and at least one barrier layer; a clad layer formed adjacent to the active layer; and a tunneling barrier layer formed between the active layer and the clad layer to be connected to the quantum well layer and formed of a material having a band-gap energy larger than the barrier layer, whereby it is possible to improve the drive characteristics at a high temperature and a high drive current by increasing a confinement effect of carriers such as electrons and holes in the active layer.

    摘要翻译： 本发明提供一种光半导体装置，包括：有源层，具有至少一个量子阱层和至少一个阻挡层; 与活性层相邻形成的覆层; 以及形成在有源层和包层之间的隧道势垒层，以与量子阱层连接并由具有比阻挡层大的带隙能量的材料形成，从而可以提高在 通过增加载体如电子和空穴在活性层中的约束效应，可以提高高温和高驱动电流。

    Coherent tuning apparatus for optical communication device
    3.
    发明申请
    Coherent tuning apparatus for optical communication device 审中-公开
    用于光通信设备的相干调谐装置

    公开(公告)号：US20050141571A1

    公开(公告)日：2005-06-30

    申请号：US10923834

    申请日：2004-08-24

    申请人： Sahnggi Park ,  Moon Park ,  Ki Kim ,  Su Oh ,  Ji Lee ,  Chul Lee

    发明人： Sahnggi Park ,  Moon Park ,  Ki Kim ,  Su Oh ,  Ji Lee ,  Chul Lee

    IPC分类号： H01S5/125 ,  H01S3/10 ,  H01S5/042 ,  H01S5/0625

    CPC分类号： H01S5/06256 ,  H01S5/0425

    摘要： Provided is a coherent tuning apparatus capable of continuously tuning wavelength of light over a wide band of wavelength at high speed and outputting high power, the apparatus including an optical waveguide through which spatially coherent light passes, an electrode array for changing a direction of the light passing through the optical waveguide by applying electric field or current to a portion of the optical waveguide, and a wavelength selection optical element unit for selecting a specific wavelength of the light.

    摘要翻译： 提供一种相干调谐装置，其能够以高速连续地调整宽波长波长的光的波长并输出高功率，该装置包括空间相干光通过的光波导，用于改变光的方向的电极阵列 通过对光波导施加电场或电流通过光波导，以及用于选择光的特定波长的波长选择光学元件单元。

    Recessed transistor and method of manufacturing the same
    4.
    发明授权
    Recessed transistor and method of manufacturing the same 有权
    嵌入式晶体管及其制造方法

    公开(公告)号：US09012982B2

    公开(公告)日：2015-04-21

    申请号：US12068179

    申请日：2008-02-04

    申请人： Keun-Nam Kim ,  Makoto Yoshida ,  Chul Lee ,  Dong-Gun Park ,  Woun-Suck Yang

    发明人： Keun-Nam Kim ,  Makoto Yoshida ,  Chul Lee ,  Dong-Gun Park ,  Woun-Suck Yang

    IPC分类号： H01L29/66 ,  H01L29/78

    CPC分类号： H01L29/66795 ,  H01L29/66621 ,  H01L29/7834 ,  H01L29/7851

    摘要： A recessed transistor and a method of manufacturing the same are provided. The recessed transistor may include a substrate, an active pin, a gate pattern and source and drain regions. The substrate may include an isolation layer that establishes an active region and a field region of the substrate. The substrate may include a recessed structure having an upper recess formed in the active region and a lower recess in communication with the upper recess. An active pin may be formed in a region between side surfaces of the isolation layer and the lower recess and an interface between the active region and the field region. The gate pattern may include a gate insulation layer formed on an inner surface of the recessed structure and a gate electrode formed on the gate insulation layer in the recessed structure. The source/drain regions may be formed adjacent to the active region and the gate electrode.

    摘要翻译： 提供凹陷晶体管及其制造方法。 凹陷的晶体管可以包括衬底，有源引脚，栅极图案以及源极和漏极区域。 衬底可以包括建立衬底的有源区和场区的隔离层。 衬底可以包括具有形成在有源区域中的上凹部的凹陷结构和与上凹部连通的下凹部。 有源销可以形成在隔离层和下凹部的侧表面之间的区域中以及有源区域和场区域之间的界面。 栅极图案可以包括形成在凹陷结构的内表面上的栅极绝缘层和形成在凹陷结构中的栅极绝缘层上的栅电极。 源/漏区可以与有源区和栅电极相邻形成。

    Semiconductor Devices Including Transistors Having Three Dimensional Channels
    9.
    发明申请
    Semiconductor Devices Including Transistors Having Three Dimensional Channels 审中-公开
    包括具有三维通道的晶体管的半导体器件

    公开(公告)号：US20080315282A1

    公开(公告)日：2008-12-25

    申请号：US12199237

    申请日：2008-08-27

    申请人： Eun-Suk Cho ,  Chul Lee

    发明人： Eun-Suk Cho ,  Chul Lee

    IPC分类号： H01L29/788

    CPC分类号： H01L23/485 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7853 ,  H01L29/7854 ,  H01L2029/7858 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Semiconductor devices including a gate electrode crossing over a semiconductor fin on a semiconductor substrate are provided. A gate insulating layer is provided between the gate electrode and the semiconductor fin. A channel region having a three-dimensional structure defined at the semiconductor fin under the gate electrode is also provided. Doped region is provided in the semiconductor fin at either side of the gate electrode and an interlayer insulating layer is provided on a surface of the semiconductor substrate. A connector region is coupled to the doped region and provided in an opening, which penetrates the interlayer insulating layer. A recess region is provided in the doped region and is coupled to the connector region. The connector region contacts an inner surface of the recess region. Related methods of fabricating semiconductor devices are also provided herein.

    摘要翻译： 提供包括在半导体衬底上与半导体鳍状物交叉的栅电极的半导体器件。 栅极绝缘层设置在栅电极和半导体鳍之间。 还提供了在栅电极下方的半导体鳍片处限定的具有三维结构的沟道区域。 掺杂区域设置在栅电极的任一侧的半导体鳍片中，并且在半导体衬底的表面上设置层间绝缘层。 连接器区域耦合到掺杂区域并且设置在穿过层间绝缘层的开口中。 在掺杂区域中提供凹陷区域并且耦合到连接器区域。 连接器区域接触凹部区域的内表面。 本文还提供了制造半导体器件的相关方法。

    Fin field effect transistor device and method of fabricating the same
    10.
    发明授权
    Fin field effect transistor device and method of fabricating the same 失效
    Fin场效应晶体管器件及其制造方法

    公开(公告)号：US07323375B2

    公开(公告)日：2008-01-29

    申请号：US11091457

    申请日：2005-03-28

    申请人： Jae-Man Yoon ,  Dong-Gun Park ,  Choong-Ho Lee ,  Chul Lee

    发明人： Jae-Man Yoon ,  Dong-Gun Park ,  Choong-Ho Lee ,  Chul Lee

    IPC分类号： H01L21/00

    CPC分类号： H01L29/7851 ,  H01L21/84 ,  H01L29/66795

    摘要： Methods of forming field effect transistors (FETs) having fin-shaped active regions include patterning a semiconductor substrate to define a fin-shaped semiconductor active region therein, which is surrounded by a trench. At least an upper portion of the fin-shaped semiconductor active region is covered with a sacrificial layer. This sacrificial layer is selectively etched-back to define sacrificial spacers on sidewalls of the fin-shaped semiconductor active region. The electrically insulating region is formed on the sacrificial spacers. The sacrificial spacers are then removed by selectively etching the sacrificial spacers using the electrically insulating region as an etching mask. An insulated gate electrode is then formed on the sidewalls of the fin-shaped semiconductor active region.

    摘要翻译： 形成具有鳍状有源区的场效应晶体管（FET）的方法包括图案化半导体衬底以在其中限定由沟槽包围的鳍状半导体有源区。 鳍形半导体有源区域的至少上部被牺牲层覆盖。 该牺牲层被有选择地回蚀刻以在鳍状半导体有源区域的侧壁上限定牺牲隔离物。 电绝缘区域形成在牺牲间隔物上。 然后通过使用电绝缘区域作为蚀刻掩模选择性地蚀刻牺牲隔离物来去除牺牲间隔物。 然后在鳍状半导体有源区的侧壁上形成绝缘栅电极。