公开(公告)号：US09818707B2

公开(公告)日：2017-11-14

申请号：US14960909

申请日：2015-12-07

申请人： Ki-Seok Oh ,  Doo-Hee Hwang ,  Dong-Yang Lee ,  Jong-Hyun Choi

发明人： Ki-Seok Oh ,  Doo-Hee Hwang ,  Dong-Yang Lee ,  Jong-Hyun Choi

IPC分类号： H01L23/52 ,  H01L23/00 ,  H01L25/065 ,  H01L27/18 ,  H01L45/00 ,  H01L27/22 ,  H01L27/24 ,  G11C7/10

CPC分类号： H01L24/06 ,  G11C7/1051 ,  G11C7/1078 ,  G11C2207/105 ,  H01L25/0657 ,  H01L27/18 ,  H01L27/222 ,  H01L27/2481 ,  H01L45/04 ,  H01L45/06 ,  H01L45/10 ,  H01L2224/09515 ,  H01L2224/73257 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06565 ,  H01L2924/1434

摘要： A stacked memory chip includes a chip input-output pad unit, a first semiconductor die and a second semiconductor die. The chip input-output pad unit includes a chip command-address pad unit, a lower chip data pad unit and an upper chip data pad unit that are to be connected to an external device. The first semiconductor die electrically is connected to the chip command-address pad unit and the lower chip data pad unit and electrically disconnected from the upper chip data pad unit. The second semiconductor die electrically is connected to the chip command-address pad unit and the upper chip data pad unit and electrically disconnected from the lower chip data pad unit. The input-output load may be reduced by selectively connecting each of the stacked semiconductor dies to one of the lower chip data pad unit and the upper chip data pad unit.

公开(公告)号：US08928349B2

公开(公告)日：2015-01-06

申请号：US13755418

申请日：2013-01-31

申请人： Ki-Seok Oh ,  Joon-Young Park ,  Yong-Hun Ahn ,  Yong-Cheol Bae ,  Yong-Gwon Jeong ,  Jong-Hyun Choi

发明人： Ki-Seok Oh ,  Joon-Young Park ,  Yong-Hun Ahn ,  Yong-Cheol Bae ,  Yong-Gwon Jeong ,  Jong-Hyun Choi

IPC分类号： H03K17/16 ,  H03K19/003 ,  H03K19/0175 ,  H04L25/02 ,  G11C7/10

CPC分类号： H03K19/017545 ,  G11C7/1057 ,  G11C2207/2272 ,  H03K19/0175 ,  H04L25/0264

摘要： An ODT circuit is activated/deactivated in response to a latency control signal or a clock enable signal. The ODT circuit includes an ODT control circuit and an ODT section. The ODT control circuit determines an ODT status based on a read latency control signal (RL) and/or a write latency control signal (WL) to generate an ODT control signal. The ODT section is activated/deactivated in response to the ODT control signal.

摘要翻译： 响应延迟控制信号或时钟使能信号，ODT电路被激活/去激活。 ODT电路包括ODT控制电路和ODT部分。 ODT控制电路基于读等待时间控制信号（RL）和/或写等待时间控制信号（WL）来确定ODT状态，以产生ODT控制信号。 响应于ODT控制信号，ODT部分被激活/去激活。

公开(公告)号：US08120971B2

公开(公告)日：2012-02-21

申请号：US12581186

申请日：2009-10-19

申请人： Ki-Seok Oh ,  Young-Sun Min

发明人： Ki-Seok Oh ,  Young-Sun Min

IPC分类号： G11C7/06

CPC分类号： G11C5/146 ,  G11C5/145

摘要： An internal source voltage generating circuit includes a comparison voltage generator which receives reference and internal source voltages, outputs to a second node a comparison voltage differentially amplified responsive to a voltage of a first node according to a difference between the reference and internal source voltages, and allows a driving current to flow from a third node to a fourth node. An internal voltage driver transfers an external source voltage to an output node responsive to the comparison voltage. A driving current generator increases the driving current flowing from the third node to the fourth node responsive to the voltage of the first node which rises when the internal source voltage abruptly drops. The internal source voltage generating circuit is insensitive to variation of an external source voltage, exhibits improved response time when an internal source voltage abruptly drops, and stably generates an internal source voltage.

摘要翻译： 内部源极电压产生电路包括比较电压发生器，其接收参考和内部源极电压，根据参考和内部源极电压之间的差异，向第二个节点输出响应于第一个节点的电压差分放大的比较电压;以及 允许驱动电流从第三节点流向第四节点。 内部电压驱动器响应于比较电压将外部源电压传送到输出节点。 驱动电流发生器响应于当内部源电压突然下降时上升的第一节点的电压，增加从第三节点流向第四节点的驱动电流。 内部源极电压发生电路对外部源极电压的变化不敏感，当内部源极电压突然下降时，表现出改善的响应时间，并稳定地产生内部源极电压。