Bit error rate estimation and classification in NAND flash memory

    公开(公告)号:US12176044B1

    公开(公告)日:2024-12-24

    申请号:US18123232

    申请日:2023-03-17

    Abstract: A method for reading data from an SSD, comprising: retrieving data from a target row of memory cells using initial threshold voltages; decoding the data using a first hard decision decoding stage; estimating a bit error rate (BER) of a target row of memory cells based on a distribution of threshold voltages of cells in a memory block containing the target row when the first hard decision decoding stage fails; classifying the BER of the target row based on a first BER threshold (BER-TH1); and executing a first read flow comprising at least one hard decision decoding stage if the BER is less than the BER-TH1, and executing a second read flow similar to the first read flow if the BER is greater than or equal to the BER-TH1, the second read flow skipping a hard decision decoding stage of the first read flow.

    System and method for pre-soft-decoding tracking for NAND flash memories

    公开(公告)号:US12039191B2

    公开(公告)日:2024-07-16

    申请号:US17574929

    申请日:2022-01-13

    Inventor: Hanan Weingarten

    CPC classification number: G06F3/0655 G06F3/0604 G06F3/0679

    Abstract: A flash memory system may include a flash memory and a circuit for performing operations on the flash memory. The circuit may be configured to obtain a first soft read sample by performing a first read operation on a location of the flash memory with a first reference voltage. The circuit may be configured to determine a second reference voltage based on the first soft read sample. The circuit may be configured to obtain a second soft read sample by performing a second read operation on the location of the flash memory with the second reference voltage. The circuit may be configured to generate soft information based on the first and second soft read samples. The circuit may be configured to decode a result of a third read operation on the location of the flash memory based on the soft information.

    SYSTEM AND METHOD FOR PRE-SOFT-DECODING TRACKING FOR NAND FLASH MEMORIES

    公开(公告)号:US20240370199A1

    公开(公告)日:2024-11-07

    申请号:US18772885

    申请日:2024-07-15

    Inventor: Hanan Weingarten

    Abstract: A flash memory system may include a flash memory and a circuit for performing operations on the flash memory. The circuit may be configured to obtain a first soft read sample by performing a first read operation on a location of the flash memory with a first reference voltage. The circuit may be configured to determine a second reference voltage based on the first soft read sample. The circuit may be configured to obtain a second soft read sample by performing a second read operation on the location of the flash memory with the second reference voltage. The circuit may be configured to generate soft information based on the first and second soft read samples. The circuit may be configured to decode a result of a third read operation on the location of the flash memory based on the soft information.

    HARD DECODING METHODS IN DATA STORAGE DEVICES

    公开(公告)号:US20230085730A1

    公开(公告)日:2023-03-23

    申请号:US18070056

    申请日:2022-11-28

    Abstract: Various implementations described herein relate to systems and methods for decoding data stored in a non-volatile storage device, including determining error candidates and determining whether at least one first error candidate from the error candidates is found based on two of the component codes agreeing on a same error candidate. In addition, whether at least one second error candidate is found based on two of the component codes agreeing on a same error candidate is determined in response to implementing a suggested correction at one of the error candidates. Errors in the data are corrected based on at least one of whether the at least one first error candidate is found or whether the at least one second error candidate is found.

    Decoding scheme for error correction code structure in data storage devices

    公开(公告)号:US11082069B1

    公开(公告)日:2021-08-03

    申请号:US16843774

    申请日:2020-04-08

    Abstract: Various implementations described herein relate to systems and methods for decoding data stored in a non-volatile storage device, including determining features for each of a plurality of component codes corresponding to the data by decoding each of the plurality of component codes, determining an extrinsic value output for each of the component codes based on the features, and after the extrinsic value output for each of the component codes is determined, decoding each of the plurality of component codes based on the extrinsic value outputs of all other component codes of the component codes. Each of the component codes depends on all other component codes.

    Deep neural network implementation for concatenated codes

    公开(公告)号:US12176924B2

    公开(公告)日:2024-12-24

    申请号:US18184916

    申请日:2023-03-16

    Abstract: Systems, methods, non-transitory computer-readable media configured to perform operations associated with a storage medium. One system includes the storage medium and an encoding/decoding (ED) system, the ED system being configured to receive a set of input log-likelihood ratios (LLRs) of a component of the plurality of components, determine an extrinsic estimation function based on a set of features of the set of input LLRs, analyze the extrinsic estimation function to obtain a plurality of extrinsic LLR values, map the plurality of extrinsic LLR values to an input LLR of the set of input LLRs, and output, for each component, a plurality of updated LLR values based on the mapping.

    EFFICIENT DECODING SCHEMES FOR ERROR CORRECTING CODES FOR MEMORY DEVICES

    公开(公告)号:US20230253985A1

    公开(公告)日:2023-08-10

    申请号:US17586290

    申请日:2022-01-27

    CPC classification number: H03M13/1128 H03M13/152 H03M13/1108 H03M13/1125

    Abstract: A system for decoding data stored in a non-volatile storage device may include processing circuits configured to decode, in a first iteration, each of a plurality of component codes corresponding to the data by performing a first number of enumerations over hypotheses. The processing circuits may be configured to determine, in the first iteration, an extrinsic value output for each of the component codes based on log-likelihood ratios (LLRs) of one or more error bits of a codeword. The processing circuits may be configured to determine a second number of enumerations based on the extrinsic value. The processing circuits may be configured to decode, in a second iteration, each of the plurality of component codes by performing the second number of enumerations over hypotheses.

    System and method for high reliability fast RAID decoding for NAND flash memories

    公开(公告)号:US11563450B1

    公开(公告)日:2023-01-24

    申请号:US16818969

    申请日:2020-03-13

    Abstract: A flash memory system may include a flash memory and a circuit for decoding a result of a read operation on the flash memory using a first codeword. The circuit may be configured to generate an estimated codeword based on a result of hard decoding the first codeword and a result of hard decoding a second codeword. The circuit may be further configured to generate soft information based on the hard decoding result of the first codeword and the estimated codeword. The circuit may be further configured to decode the result of the read operation on the flash memory using the soft information.

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