公开(公告)号：US07906410B2

公开(公告)日：2011-03-15

申请号：US12160482

申请日：2008-02-07

申请人： Kiyoshi Arita ,  Atsushi Harikai

发明人： Kiyoshi Arita ,  Atsushi Harikai

IPC分类号： H01L21/00

CPC分类号： H01L21/78 ,  H01L21/6836 ,  H01L2221/68327 ,  H01L2221/68377 ,  H01L2221/68381

摘要： In a method in which a semiconductor wafer 1 having integrated circuits 3 formed in a plurality of chip regions and test patterns 4 formed in scribe lines 2a is divided by a plasma etching process so as to manufacture individual semiconductor chips, in the semiconductor wafer 1, a protection sheet 5 which constitutes a mask in the plasma etching process is adhered onto a front plane 1a thereof where the integrated circuits 3 have been formed; since laser light 9a is irradiated along the scribe lines 2a, only a predetermined width of the protection sheet 5 is removed so as to form a mask having a plasma dicing-purpose opening portion 5b; and also, the test patterns 4 are removed by the laser light 9a in combination with a front plane layer of the semiconductor wafer 1. As a result, the test patterns 4 can be removed in a higher efficiency and in simple steps, while the general purpose characteristic can be secured.

摘要翻译： 在形成有多个芯片区域的集成电路3的半导体晶片1和划线2a所形成的测试图案4通过等离子体蚀刻工艺进行分割以制造各个半导体芯片的方法中，在半导体晶片1中， 在等离子体蚀刻工艺中构成掩模的保护片5粘附到已经形成集成电路3的前面1a上; 由于沿着划线2a照射激光9a，所以仅去除保护片5的规定宽度，形成具有等离子体切割用开口部5b的掩模; 并且还通过与半导体晶片1的正面层组合的激光9a去除测试图案4.结果，可以以更高的效率和简单的步骤去除测试图案4，而一般 可以确保目的特性。

公开(公告)号：US07994026B2

公开(公告)日：2011-08-09

申请号：US12523191

申请日：2008-11-12

申请人： Atsushi Harikai ,  Kiyoshi Arita ,  Tetsuhiro Iwai

发明人： Atsushi Harikai ,  Kiyoshi Arita ,  Tetsuhiro Iwai

IPC分类号： H01L21/301

CPC分类号： H01L21/67069 ,  H01J37/32743 ,  H01J37/32788 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/78

摘要： A plasma dicing apparatus in which a semiconductor wafer with a protective sheet stuck thereonto covering the entire circuit-forming surface and with an etching-resistant mask member stuck on the back surface opposite to the circuit-forming surface is mounted on a mounting stage; plasma etching is performed using the mask member as a mask; and the semiconductor wafer is diced into plural semiconductor chips. The plasma dicing apparatus includes a ring-shaped frame member retaining the outer circumference of the mask member extending off the outer circumference of the semiconductor wafer. The mounting stage is composed of a wafer supporting part supporting a semiconductor wafer and a frame member supporting part supporting the frame member. This facilitates carrying a semiconductor wafer into and out of the vacuum chamber.

摘要翻译： 一种等离子体切割装置，其中具有粘附在其上以覆盖整个电路形成表面的保护片的半导体晶片和粘附在与电路形成表面相对的背面上的耐蚀刻掩模构件安装在安装台上; 使用掩模构件作为掩模进行等离子体蚀刻; 将半导体晶片切割成多个半导体芯片。 等离子体切割装置包括保持从半导体晶片的外周延伸的掩模构件的外周的环形框架构件。 安装台由支撑半导体晶片的晶片支撑部件和支撑框架部件的框架部件支撑部件构成。 这有助于将半导体晶片进入和离开真空室。

公开(公告)号：US20100197115A1

公开(公告)日：2010-08-05

申请号：US12667318

申请日：2008-08-07

申请人： Kiyoshi Arita ,  Atsushi Harikai

发明人： Kiyoshi Arita ,  Atsushi Harikai

IPC分类号： H01L21/78

CPC分类号： H01L21/78 ,  H01L21/6835 ,  H01L21/6836 ,  H01L2221/68327 ,  H01L2221/68336

摘要： To provide a method of segmenting a semiconductor wafer, which is capable of preventing chippings.A semiconductor wafer 1 is partitioned into a circumferential ring-shaped region 1a and a segmentation region placed in the inner side of the ring-shaped region 1a. The semiconductor wafer 1 included in the segmentation region is cut into the form of a lattice along a plurality of perpendicular cutting lines 4 and is segmented into a plurality of chips 2. On the other hand, the semiconductor wafer 1 included in the ring-shaped region 1a is cut along two partition lines 5 extending in parallel to the cutting lines 4 from the center O of the semiconductor wafer 1 and is partitioned into four independent regions.

摘要翻译： 提供能够防止切屑的半导体晶片的分割方法。 将半导体晶片1分割成环状区域1a和设置在环状区域1a的内侧的分割区域。 包含在分割区域中的半导体晶片1沿着多个垂直切割线4被切割为格子的形式，并且被分割成多个芯片2.另一方面，包括在环形的半导体晶片1 区域1a沿着从半导体晶片1的中心O平行于切割线4延伸的两个分隔线5被切割，并且被划分为四个独立的区域。

公开(公告)号：US20100173474A1

公开(公告)日：2010-07-08

申请号：US12160482

申请日：2008-02-07

申请人： Kiyoshi Arita ,  Atsushi Harikai

发明人： Kiyoshi Arita ,  Atsushi Harikai

IPC分类号： H01L21/78

CPC分类号： H01L21/78 ,  H01L21/6836 ,  H01L2221/68327 ,  H01L2221/68377 ,  H01L2221/68381

摘要： In a method in which a semiconductor wafer 1 having integrated circuits 3 formed in a plurality of chip regions and test patterns 4 formed in scribe lines 2a is divided by a plasma etching process so as to manufacture individual semiconductor chips, in the semiconductor wafer 1, a protection seat 5 which constitutes a mask in the plasma etching process is adhered onto a front plane 1a thereof where the integrated circuits 3 have been formed; since laser light 9a is irradiated along the scribe lines 2a, only a predetermined width of the protection seat 5 is removed so as to form a mask having a plasma dicing-purpose opening portion 5b; and also, the test patterns 4 are removed by the laser light 9a in combination with a front plane layer of the semiconductor wafer 1. As a result, the test patterns 4 can be removed in a higher efficiency and in simple steps, while the general purpose characteristic can be secured.

摘要翻译： 在形成有多个芯片区域的集成电路3的半导体晶片1和划线2a所形成的测试图案4通过等离子体蚀刻工艺进行分割以制造各个半导体芯片的方法中，在半导体晶片1中， 在等离子体蚀刻工艺中构成掩模的保护座5粘附到已经形成集成电路3的前面1a上; 由于沿着划线2a照射激光9a，所以仅去除保护座5的预定宽度，形成具有等离子体切割用开口部5b的掩模; 并且还通过与半导体晶片1的正面层组合的激光9a去除测试图案4.结果，可以以更高的效率和简单的步骤去除测试图案4，而一般 可以确保目的特性。

公开(公告)号：US20100048001A1

公开(公告)日：2010-02-25

申请号：US12523191

申请日：2008-11-12

申请人： Atsushi Harikai ,  Kiyoshi Arita ,  Tetsuhiro Iwai

发明人： Atsushi Harikai ,  Kiyoshi Arita ,  Tetsuhiro Iwai

IPC分类号： H01L21/302 ,  H01L21/3065

CPC分类号： H01L21/67069 ,  H01J37/32743 ,  H01J37/32788 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/78

摘要： A plasma dicing apparatus in which a semiconductor wafer with a protective sheet stuck thereonto covering the entire circuit-forming surface and with an etching-resistant mask member stuck on the back surface opposite to the circuit-forming surface is mounted on a mounting stage; plasma etching is performed using the mask member as a mask; and the semiconductor wafer is diced into plural semiconductor chips. The plasma dicing apparatus includes a ring-shaped frame member retaining the outer circumference of the mask member extending off the outer circumference of the semiconductor wafer. The mounting stage is composed of a wafer supporting part supporting a semiconductor wafer and a frame member supporting part supporting the frame member. This facilitates carrying a semiconductor wafer into and out of the vacuum chamber.

摘要翻译： 一种等离子体切割装置，其中具有粘附在其上以覆盖整个电路形成表面的保护片的半导体晶片和粘附在与电路形成表面相对的背面上的耐蚀刻掩模构件安装在安装台上; 使用掩模构件作为掩模进行等离子体蚀刻; 将半导体晶片切割成多个半导体芯片。 等离子体切割装置包括保持从半导体晶片的外周延伸的掩模构件的外周的环形框架构件。 安装台由支撑半导体晶片的晶片支撑部件和支撑框架部件的框架部件支撑部件构成。 这有助于将半导体晶片进入和离开真空室。

公开(公告)号：US08110481B2

公开(公告)日：2012-02-07

申请号：US12667318

申请日：2008-08-07

申请人： Kiyoshi Arita ,  Atsushi Harikai

发明人： Kiyoshi Arita ,  Atsushi Harikai

IPC分类号： H01L21/00

CPC分类号： H01L21/78 ,  H01L21/6835 ,  H01L21/6836 ,  H01L2221/68327 ,  H01L2221/68336

摘要： To provide a method of segmenting a semiconductor wafer, which is capable of preventing chippings.A semiconductor wafer 1 is partitioned into a circumferential ring-shaped region 1a and a segmentation region placed in the inner side of the ring-shaped region 1a. The semiconductor wafer 1 included in the segmentation region is cut into the form of a lattice along a plurality of perpendicular cutting lines 4 and is segmented into a plurality of chips 2. On the other hand, the semiconductor wafer 1 included in the ring-shaped region 1a is cut along two partition lines 5 extending in parallel to the cutting lines 4 from the center O of the semiconductor wafer 1 and is partitioned into four independent regions.

摘要翻译： 提供能够防止切屑的半导体晶片的分割方法。 将半导体晶片1分割成环状区域1a和设置在环状区域1a的内侧的分割区域。 包含在分割区域中的半导体晶片1沿着多个垂直切割线4被切割为格子的形式，并且被分割成多个芯片2.另一方面，包括在环形的半导体晶片1 区域1a沿着从半导体晶片1的中心O平行于切割线4延伸的两个分隔线5被切割，并且被划分为四个独立的区域。

公开(公告)号：US07767554B2

公开(公告)日：2010-08-03

申请号：US12517632

申请日：2008-03-05

申请人： Kiyoshi Arita ,  Atsushi Harikai

发明人： Kiyoshi Arita ,  Atsushi Harikai

IPC分类号： H01L21/78 ,  H01L21/46 ,  H01L21/301

CPC分类号： H01L21/78 ,  H01L21/3043 ,  H01L21/6836 ,  H01L24/27 ,  H01L24/29 ,  H01L24/83 ,  H01L2221/68322 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68359 ,  H01L2224/274 ,  H01L2224/83191 ,  H01L2224/8385 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01057 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/07802 ,  H01L2924/14 ,  H01L2924/3512 ,  H01L2924/00

摘要： An object is to provide a semiconductor chip manufacturing method capable of removing test patterns in a higher efficiency in simple steps, while a general-purpose characteristic can be secured.In a method in which a semiconductor wafer 1 having integrated circuits 3 formed in a plurality of chip regions and test patterns 4 formed in scribe lines 2a is divided by a plasma etching process so as to manufacture individual semiconductor chips, laser light 5a is irradiated from the side of a circuit forming plane 1a so as to remove the test patterns 4; and thereafter, under such a condition that a circuit protection seat 6 is adhered onto a circuit forming plane 1a, a rear plane of the circuit forming plane 1a is mechanically thinned; a mask-purpose seat is adhered onto the rear plane 1b of the semiconductor wafer 1 after the plane thinning process; and then, a plasma dicing-purpose mask is work-processed by irradiating laser light. As a consequence, the semi-conductor wafer 1 can be held by employing one set of the circuit protection seat 6 from the thinning process up to the plasma dicing process.

摘要翻译： 本发明的目的是提供一种能够以简单的步骤以更高效率去除测试图案的半导体芯片制造方法，同时可以确保通用特性。 在形成有多个芯片区域的集成电路3的半导体晶片1和划线2a所形成的测试图案4通过等离子体蚀刻工艺进行分割以制造各个半导体芯片的方法中，从 电路形成平面1a的一侧，以便去除测试图案4; 之后，在将电路保护座6粘接在电路形成面1a上的状态下，电路形成面1a的背面机械地变薄; 在平面变薄处理之后，将掩模用座椅粘附到半导体晶片1的后面1b上; 然后，通过照射激光对等离子体切割用掩模进行加工处理。 因此，半导体晶片1可以通过采用一组电路保护座6从薄化处理到等离子体切割工艺来保持。

公开(公告)号：US20100022071A1

公开(公告)日：2010-01-28

申请号：US12517632

申请日：2008-03-05

申请人： Kiyoshi Arita ,  Atsushi Harikai

发明人： Kiyoshi Arita ,  Atsushi Harikai

IPC分类号： H01L21/78

CPC分类号： H01L21/78 ,  H01L21/3043 ,  H01L21/6836 ,  H01L24/27 ,  H01L24/29 ,  H01L24/83 ,  H01L2221/68322 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68359 ,  H01L2224/274 ,  H01L2224/83191 ,  H01L2224/8385 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01057 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/07802 ,  H01L2924/14 ,  H01L2924/3512 ,  H01L2924/00

摘要： An object is to provide a semiconductor chip manufacturing method capable of removing test patterns in a higher efficiency in simple steps, while a general-purpose characteristic can be secured.In a method in which a semiconductor wafer 1 having integrated circuits 3 formed in a plurality of chip regions and test patterns 4 formed in scribe lines 2a is divided by a plasma etching process so as to manufacture individual semiconductor chips, laser light 5a is irradiated from the side of a circuit forming plane 1a so as to remove the test patterns 4; and thereafter, under such a condition that a circuit protection seat 6 is adhered onto a circuit forming plane 1a, a rear plane of the circuit forming plane 1a is mechanically thinned; a mask-purpose seat is adhered onto the rear plane 1b of the semiconductor wafer 1 after the plane thinning process; and then, a plasma dicing-purpose mask is work-processed by irradiating laser light. As a consequence, the semi-conductor wafer 1 can be held by employing one set of the circuit protection seat 6 from the thinning process up to the plasma dicing process.

摘要翻译： 本发明的目的是提供一种能够以简单的步骤以更高效率去除测试图案的半导体芯片制造方法，同时可以确保通用特性。 在形成有多个芯片区域的集成电路3的半导体晶片1和划线2a所形成的测试图案4通过等离子体蚀刻工艺进行分割以制造各个半导体芯片的方法中，从 电路形成平面1a的一侧，以便去除测试图案4; 之后，在将电路保护座6粘接在电路形成面1a上的状态下，电路形成面1a的背面机械地变薄; 在平面变薄处理之后，将掩模用座椅粘附到半导体晶片1的后面1b上; 然后，通过照射激光对等离子体切割用掩模进行加工处理。 因此，半导体晶片1可以通过采用一组电路保护座6从薄化处理到等离子体切割工艺来保持。

公开(公告)号：US20140295644A1

公开(公告)日：2014-10-02

申请号：US14117463

申请日：2012-05-18

申请人： Atsushi Harikai

发明人： Atsushi Harikai

IPC分类号： H01L21/78 ,  H01L21/683 ,  H01L21/304

CPC分类号： H01L21/78 ,  H01J37/321 ,  H01L21/0273 ,  H01L21/304 ,  H01L21/3065 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/6836 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68386

摘要： Provided is a method of manufacturing semiconductor chips superior in chip yield, reduction in chipping, and handling ability. An insulating film in a dividing region is removed by plasma etching to a front surface. Then, roughness on a resist mask formed on the front surface is removed by plasma treatment before a BG tape is attached. After a semiconductor wafer is thinned by grinding of a backside surface thereof, the BG tape is peeled. The semiconductor wafer is divided into individual semiconductor chips by plasma etching from the front surface thereof.

摘要翻译： 提供了一种制造芯片产量优异，切削削减和处理能力优异的半导体芯片的方法。 通过等离子体蚀刻去除分隔区域中的绝缘膜到前表面。 然后，在安装BG带之前，通过等离子体处理去除在前表面上形成的抗蚀剂掩模上的粗糙度。 在通过研磨其背面使半导体晶片变薄之后，剥离BG带。 半导体晶片从其前表面通过等离子体蚀刻被分成单独的半导体芯片。

公开(公告)号：US20060205139A1

公开(公告)日：2006-09-14

申请号：US11367644

申请日：2006-03-03

申请人： Masato Kijima ,  Atsushi Harikai

发明人： Masato Kijima ,  Atsushi Harikai

IPC分类号： H01L21/8238

CPC分类号： H01L23/544 ,  H01L21/823892 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method is provided for forming plural kinds of wells on a single semiconductor substrate with an improved alignment accuracy and obviating the generation of step height between the wells. The method includes forming a selective etching film on the semiconductor substrate, forming openings on the selective etching film overlying a first well forming region and an alignment mark forming region using a first resist film as a mask for defining the first well forming region and the alignment mark forming region, implanting the first well forming region with a dopant of a first conductivity type and removing the first resist film, forming a second resist film to mask at least the first well forming region, having an opening overlying the alignment mark forming region larger than the opening of the selective etching film overlying the same region, and forming the alignment mark by performing an etching process using the second resist film and selective etching film as a mask.