公开(公告)号：US20090160484A1

公开(公告)日：2009-06-25

申请号：US12004617

申请日：2007-12-21

Applicant: Kiyoshi Kase ,  May Len ,  Dzung T. Tran

Inventor： Kiyoshi Kase ,  May Len ,  Dzung T. Tran

IPC: H03K19/0175

CPC classification number: H03K19/018521

Abstract: Methods and corresponding systems for buffering an input signal include outputting a first logic value in response to the input signal being below a lower threshold. A second logic value is output in response to the input signal rising above the lower threshold. Thereafter, the second logic value is maintained until the input exceeds a higher threshold and thereafter falls below the higher threshold. In response to the input signal falling below the higher threshold, the first logic value is output, and maintained at the first logic value, until the input falls below the lower threshold and thereafter rises above the lower threshold.

Abstract translation: 用于缓冲输入信号的方法和相应系统包括响应于输入信号低于较低阈值输出第一逻辑值。 响应于输入信号上升到较低阈值以上而输出第二逻辑值。 此后，维持第二逻辑值，直到输入超过较高阈值，然后低于较高阈值。 响应于输入信号低于较高阈值，第一逻辑值被输出并保持在第一逻辑值，直到输入低于低阈值，然后上升到低于下阈值。

公开(公告)号：US07667492B2

公开(公告)日：2010-02-23

申请号：US12004617

申请日：2007-12-21

Applicant: Kiyoshi Kase ,  May Len ,  Dzung T. Tran

Inventor： Kiyoshi Kase ,  May Len ,  Dzung T. Tran

IPC: H03K19/094

CPC classification number: H03K19/018521

Abstract: Methods and corresponding systems for buffering an input signal include outputting a first logic value in response to the input signal being below a lower threshold. A second logic value is output in response to the input signal rising above the lower threshold. Thereafter, the second logic value is maintained until the input exceeds a higher threshold and thereafter falls below the higher threshold. In response to the input signal falling below the higher threshold, the first logic value is output, and maintained at the first logic value, until the input falls below the lower threshold and thereafter rises above the lower threshold.

Abstract translation: 用于缓冲输入信号的方法和相应系统包括响应于输入信号低于较低阈值输出第一逻辑值。 响应于输入信号上升到较低阈值以上而输出第二逻辑值。 此后，维持第二逻辑值，直到输入超过较高阈值，然后低于较高阈值。 响应于输入信号低于较高阈值，第一逻辑值被输出并保持在第一逻辑值，直到输入低于低阈值，然后上升到低于下阈值。

公开(公告)号：US07508246B2

公开(公告)日：2009-03-24

申请号：US11532295

申请日：2006-09-15

Applicant: Kiyoshi Kase ,  Dzung T. Tran

Inventor： Kiyoshi Kase ,  Dzung T. Tran

IPC: H03H11/26 ,  H03B1/00 ,  H03K19/094

CPC classification number: H03H11/26

Abstract: A circuit's performance may vary based on various factors such as, for example, process, voltage, and/or temperature. In one embodiment, a circuit includes an input terminal which receives an input signal, a delay selection section which delays the input signal by a delay amount selected by a performance variation indicator, an impedance selection section which outputs the delayed input signal as a compensated delayed signal, where the impedance selection section uses a driver impedance amount selected by the performance variation indicator, and an output terminal which outputs the compensated delayed signal. The circuit may also include a ring oscillator, a frequency counter which provides a count value which indicates a number of rising edges of an output of the ring oscillator which occur during a period of a reference frequency, and a decoder which uses the count value to output the performance variation indicator.

Abstract translation: 电路的性能可以基于诸如例如工艺，电压和/或温度的各种因素而变化。 在一个实施例中，电路包括接收输入信号的输入端子，延迟选择部分，其将输入信号延迟由性能变化指示器选择的延迟量;阻抗选择部分，其输出延迟的输入信号作为经补偿的延迟 信号，其中阻抗选择部分使用由性能变化指示器选择的驱动器阻抗量，以及输出端子，其输出经补偿的延迟信号。 电路还可以包括环形振荡器，频率计数器，其提供指示在参考频率的周期期间发生的环形振荡器的输出的上升沿的数量的计数值;以及解码器，其使用计数值 输出性能变化指标。

公开(公告)号：US07479813B2

公开(公告)日：2009-01-20

申请号：US11424132

申请日：2006-06-14

Applicant: Kiyoshi Kase ,  Dzung T. Tran ,  May Len

Inventor： Kiyoshi Kase ,  Dzung T. Tran ,  May Len

IPC: H03B1/00 ,  H03K3/00

CPC classification number: G05F3/205

Abstract: In one form a circuit has a bias stage having an input signal terminal for receiving an input signal. The circuit modifies the input signal with a drive stage to provide an output signal in complement form. A drive transistor in the drive stage of the circuit has a bulk that is connected to a terminal of a load and to a control electrode coupled to the input signal terminal. A bias transistor in the bias stage of the circuit has a bulk that is directly connected to the terminal of the load and to the bulk of the drive transistor. The bias transistor has a control electrode coupled to the input signal terminal. The input signal biases the bulks of the drive transistor and the bias transistor and reduces transistor threshold voltage. Linearity of circuit output impedance is improved and RF interference reduced. Lower voltage operation is also provided.

Abstract translation: 在一种形式中，电路具有偏置级，其具有用于接收输入信号的输入信号端子。 该电路用驱动级修改输入信号以提供补码形式的输出信号。 电路的驱动级中的驱动晶体管具有连接到负载的端子和耦合到输入信号端子的控制电极的体积。 电路的偏置级中的偏置晶体管具有直接连接到负载的端子和驱动晶体管体的体积。 偏置晶体管具有耦合到输入信号端子的控制电极。 输入信号偏置驱动晶体管和偏置晶体管的体积，并降低晶体管阈值电压。 电路输出阻抗的线性提高，RF干扰降低。 还提供较低的电压操作。

公开(公告)号：US07420394B2

公开(公告)日：2008-09-02

申请号：US11561209

申请日：2006-11-17

Applicant: Kiyoshi Kase ,  Dzung T. Tran

Inventor： Kiyoshi Kase ,  Dzung T. Tran

IPC: H03K19/094

CPC classification number: H03K3/3565

Abstract: An input buffer circuit with hysteresis includes a first stage and a second stage. The first stage includes a resistive device to provide a resistance between two nodes of the first stage. The two nodes are responsive to a signal input. The second stage includes four series-coupled transistors. A first node is coupled to the control electrodes of two of the four transistors and the second node is coupled to the control electrodes of the other two transistors. The second stage includes a signal output. In some examples, a resistance provided by the resistive device is variable and provides the buffer circuit with hysteresis.

Abstract translation: 具有迟滞的输入缓冲电路包括第一级和第二级。 第一级包括用于在第一级的两个节点之间提供电阻的电阻装置。 两个节点响应信号输入。 第二级包括四个串联耦合晶体管。 第一节点耦合到四个晶体管中的两个的控制电极，并且第二节点耦合到另外两个晶体管的控制电极。 第二级包括信号输出。 在一些示例中，由电阻装置提供的电阻是可变的并且为缓冲电路提供迟滞。

公开(公告)号：US20080122520A1

公开(公告)日：2008-05-29

申请号：US11424132

申请日：2006-06-14

Applicant: Kiyoshi Kase ,  Dzung T. Tran ,  May Len

Inventor： Kiyoshi Kase ,  Dzung T. Tran ,  May Len

IPC: G05F3/02

CPC classification number: G05F3/205

Abstract: In one form a circuit has a bias stage having an input signal terminal for receiving an input signal. The circuit modifies the input signal with a drive stage to provide an output signal in complement form. A drive transistor in the drive stage of the circuit has a bulk that is connected to a terminal of a load and to a control electrode coupled to the input signal terminal. A bias transistor in the bias stage of the circuit has a bulk that is directly connected to the terminal of the load and to the bulk of the drive transistor. The bias transistor has a control electrode coupled to the input signal terminal. The input signal biases the bulks of the drive transistor and the bias transistor and reduces transistor threshold voltage. Linearity of circuit output impedance is improved and RF interference reduced. Lower voltage operation is also provided.

Abstract translation: 在一种形式中，电路具有偏置级，其具有用于接收输入信号的输入信号端子。 该电路用驱动级修改输入信号以提供补码形式的输出信号。 电路的驱动级中的驱动晶体管具有连接到负载的端子和耦合到输入信号端子的控制电极的体积。 电路的偏置级中的偏置晶体管具有直接连接到负载的端子和驱动晶体管体的体积。 偏置晶体管具有耦合到输入信号端子的控制电极。 输入信号偏置驱动晶体管和偏置晶体管的体积，并降低晶体管阈值电压。 电路输出阻抗的线性提高，RF干扰降低。 还提供较低的电压操作。

公开(公告)号：US20080116952A1

公开(公告)日：2008-05-22

申请号：US11561209

申请日：2006-11-17

Applicant: Kiyoshi Kase ,  Dzung T. Tran

Inventor： Kiyoshi Kase ,  Dzung T. Tran

IPC: H03K3/01

CPC classification number: H03K3/3565

Abstract: An input buffer circuit with hysteresis includes a first stage and a second stage. The first stage includes a resistive device to provide a resistance between two nodes of the first stage. The two nodes are responsive to a signal input. The second stage includes four series-coupled transistors. A first node is coupled to the control electrodes of two of the four transistors and the second node is coupled to the control electrodes of the other two transistors. The second stage includes a signal output. In some examples, a resistance provided by the resistive device is variable and provides the buffer circuit with hysteresis.

Abstract translation: 具有迟滞的输入缓冲电路包括第一级和第二级。 第一级包括用于在第一级的两个节点之间提供电阻的电阻装置。 两个节点响应信号输入。 第二级包括四个串联耦合晶体管。 第一节点耦合到四个晶体管中的两个的控制电极，并且第二节点耦合到另外两个晶体管的控制电极。 第二级包括信号输出。 在一些示例中，由电阻装置提供的电阻是可变的并且为缓冲电路提供迟滞。

公开(公告)号：US07002371B2

公开(公告)日：2006-02-21

申请号：US10747748

申请日：2003-12-29

Applicant: Kiyoshi Kase ,  May Len ,  Dzung T. Tran

Inventor： Kiyoshi Kase ,  May Len ,  Dzung T. Tran

IPC: H03K19/094

CPC classification number: H03K17/102 ,  H03K3/356008 ,  H03K3/356113

Abstract: A level shifter with cross coupled inverters having different threshold voltages. The output of the level shifter is pulled to a known voltage state during power up. In some examples, one of the inverters includes an additional N-channel transistor wherein the threshold voltage is greater the threshold voltage of the other inverter due to the additional transistor.

Abstract translation: 具有不同阈值电压的交叉耦合反相器的电平移位器。 在上电期间，电平转换器的输出被拉到已知的电压状态。 在一些示例中，一个反相器包括附加的N沟道晶体管，其中由于附加晶体管，阈值电压大于另一个反相器的阈值电压。

公开(公告)号：US20090237164A1

公开(公告)日：2009-09-24

申请号：US12053754

申请日：2008-03-24

Applicant: Kiyoshi Kase ,  Dzung T. Tran

Inventor： Kiyoshi Kase ,  Dzung T. Tran

IPC: H03F3/45

CPC classification number: H03K17/04206 ,  H03K17/063

Abstract: A circuit includes first, second, and third inverters and first and second transistors. The first inverter has an input, an output, a first supply terminal, and a second supply terminal. The second inverter has an input, an output, a first supply terminal, and a second supply terminal. The first transistor has a first current electrode for receiving a first supply voltage, a control electrode coupled to the output of the first inverter, and a second current electrode coupled to the first supply terminals of both the first and second inverters. The second transistor has a first current electrode coupled to the second supply terminals of the first and second inverters, a control electrode coupled to the output of the first inverter, and a second current electrode for receiving a second supply voltage. The third inverter has an input coupled to the output of the second inverter, and an output coupled to the output of the first inverter.

Abstract translation: 电路包括第一，第二和第三反相器以及第一和第二晶体管。 第一逆变器具有输入端，输出端，第一供电端子和第二供电端子。 第二逆变器具有输入端，输出端，第一供电端子和第二供电端子。 第一晶体管具有用于接收第一电源电压的第一电流电极，耦合到第一反相器的输出的控制电极和耦合到第一和第二逆变器的第一电源端子的第二电流电极。 第二晶体管具有耦合到第一和第二反相器的第二电源端的第一电流电极，耦合到第一反相器的输出的控制电极和用于接收第二电源电压的第二电流电极。 第三反相器具有耦合到第二反相器的输出的输入端和耦合到第一反相器的输出的输出。

公开(公告)号：US20080068061A1

公开(公告)日：2008-03-20

申请号：US11532295

申请日：2006-09-15

Applicant: Kiyoshi Kase ,  Dzung T. Tran

Inventor： Kiyoshi Kase ,  Dzung T. Tran

IPC: H03H11/26

CPC classification number: H03H11/26

Abstract: A circuit's performance may vary based on various factors such as, for example, process, voltage, and/or temperature. In one embodiment, a circuit includes an input terminal which receives an input signal, a delay selection section which delays the input signal by a delay amount selected by a performance variation indicator, an impedance selection section which outputs the delayed input signal as a compensated delayed signal, where the impedance selection section uses a driver impedance amount selected by the performance variation indicator, and an output terminal which outputs the compensated delayed signal. The circuit may also include a ring oscillator, a frequency counter which provides a count value which indicates a number of rising edges of an output of the ring oscillator which occur during a period of a reference frequency, and a decoder which uses the count value to output the performance variation indicator.

Abstract translation: 电路的性能可以基于诸如例如工艺，电压和/或温度的各种因素而变化。 在一个实施例中，电路包括接收输入信号的输入端子，延迟选择部分，其将输入信号延迟由性能变化指示器选择的延迟量;阻抗选择部分，其输出延迟的输入信号作为经补偿的延迟 信号，其中阻抗选择部分使用由性能变化指示器选择的驱动器阻抗量，以及输出端子，其输出经补偿的延迟信号。 电路还可以包括环形振荡器，频率计数器，其提供指示在参考频率的周期期间发生的环形振荡器的输出的上升沿的数量的计数值;以及解码器，其使用计数值 输出性能变化指标。