公开(公告)号：US07899139B2

公开(公告)日：2011-03-01

申请号：US12003933

申请日：2008-01-03

申请人： Hideki Nakahara ,  Koichiro Tanaka ,  Kenichi Mori ,  Yoshio Urabe ,  Hitoshi Takai

发明人： Hideki Nakahara ,  Koichiro Tanaka ,  Kenichi Mori ,  Yoshio Urabe ,  Hitoshi Takai

IPC分类号： H04L27/06

CPC分类号： H04L7/041 ,  H04L7/0334 ,  H04L7/046 ,  H04L27/2332 ,  H04L2027/0036 ,  H04L2027/0067 ,  H04L2027/0095

摘要： A detected signal 111 contains a preamble portion which includes symbol alternations, followed by a unique word portion, and a data portion. Each time a symbol alternation is detected, a correction value calculation section 102 averages the phase shift in the detected signal 111 for a predetermined length, thereby calculating a correction value 115. The correction value determination section 103 stores a plurality of correction values 115 in a chronological order. When the unique word portion is detected, the correction value determination section 103 retains, as an effective correction value 118, a correction value which is arrived at by going back a predetermined number of correction values among the stored correction values. A phase rotation section 104 corrects the phase of the detected signal 111 by using an effective correction value 118 calculated by the correction value determination section 103.

摘要翻译： 检测信号111包含前导码部分，其包括符号替换，随后是唯一字部分和数据部分。 每当检测到符号交替时，校正值计算部分102将检测信号111中的相移平均预定长度，从而计算校正值115.校正值确定部分103将多个校正值115存储在 按时间顺序排列。 当检测到唯一字部分时，校正值确定部分103将存储的校正值中的预定数量的校正值返回到达到的校正值作为有效校正值118。 相位旋转部104通过使用由校正值确定部103计算出的有效校正值118来校正检测信号111的相位。

公开(公告)号：US07277501B2

公开(公告)日：2007-10-02

申请号：US10640655

申请日：2003-08-14

申请人： Kenichi Mori ,  Yoshio Urabe ,  Koichiro Tanaka ,  Hideki Nakahara ,  Hitoshi Takai

发明人： Kenichi Mori ,  Yoshio Urabe ,  Koichiro Tanaka ,  Hideki Nakahara ,  Hitoshi Takai

IPC分类号： H03D3/00 ,  H03K9/06

CPC分类号： H04L27/2331 ,  H04L5/06

摘要： A data receiving device is provided enabling a reduction in the time required for extracting a partial band signal, and capable of being easily made in a simple structure as an LSI device without requiring a plurality of analog circuits having the same characteristics. The data receiving device includes: a first sampler for sampling an in-phase signal I(t) at every predetermined sampling period and outputting the sampled in-phase signal; a second sampler for sampling a quadrature signal at every predetermined sampling period and outputting the sampled quadrature signal; a partial band extracting section structured by a complex filter for extracting partial band signals IBr, QBr from frequency components included in the sampled in-phase signal and the sampled quadrature signal; and first and second delay detection operating sections for performing a delay detecting process based on the partial band signals and outputting detection signals.

摘要翻译： 提供一种数据接收装置，其能够减少提取部分频带信号所需的时间，并且能够容易地以简单的结构作为LSI装置，而不需要具有相同特性的多个模拟电路。 数据接收装置包括：第一采样器，用于在每个预定采样周期对同相信号I（t）进行采样，并输出采样的同相信号; 第二取样器，用于在每个预定采样周期对正交信号进行采样，并输出采样的正交信号; 由复数滤波器构成的部分频带提取部分，用于从包括在采样的同相信号中的频率分量和采样的正交信号中提取部分频带信号IB，QB＆lt; SUB＆lt; ; 以及第一和第二延迟检测操作部分，用于基于部分频带信号执行延迟检测处理并输出检测信号。

公开(公告)号：US20050185727A1

公开(公告)日：2005-08-25

申请号：US11063892

申请日：2005-02-23

申请人： Koichiro Tanaka ,  Hitoshi Takai ,  Kenichi Mori

发明人： Koichiro Tanaka ,  Hitoshi Takai ,  Kenichi Mori

IPC分类号： H04L5/12 ,  H04L27/00 ,  H04L27/04 ,  H04L27/20

CPC分类号： H04L27/04 ,  H04L27/0008 ,  H04L27/206

摘要： A first signal generation section 11 generates a baseband modulation signal for an ASK modulation scheme from transmission data. A second signal generation section 12 generates a pair of baseband modulation signals for a non-ASK modulation scheme from transmission data. When performing non-ASK modulation, a switch 15 connects between an input terminal d and an output terminal and outputs the baseband modulation signals based on the non-ASK modulation. When performing ASK modulation such that the transmission power ratio of the ASK modulation scheme to the non-ASK modulation scheme is a factor of 1, a switch 14 connects between an input terminal b and an output terminal and the switch 15 connects between an input terminal c and the output terminal. When performing ASK modulation such that the transmission power ratio is a factor of 2, the switch 14 connects between an input terminal a and the output terminal and the switch 15 connects between the input terminal c and the output terminal.

摘要翻译： 第一信号生成部11从发送数据生成用于ASK调制方式的基带调制信号。 第二信号生成部分12从发送数据生成用于非ASK调制方案的一对基带调制信号。 当执行非ASK调制时，开关15在输入端子d和输出端子之间连接，并且基于非ASK调制输出基带调制信号。 当执行ASK调制使得ASK调制方案的发送功率比与非ASK调制方案的因数为1时，开关14在输入端子b和输出端子之间连接，并且开关15连接在输入端子 c和输出端子。 当执行ASK调制使得发送功率比为因子2时，开关14在输入端子a和输出端子之间连接，并且开关15连接在输入端子c和输出端子之间。

公开(公告)号：US07418047B2

公开(公告)日：2008-08-26

申请号：US11063892

申请日：2005-02-23

申请人： Koichiro Tanaka ,  Hitoshi Takai ,  Kenichi Mori

发明人： Koichiro Tanaka ,  Hitoshi Takai ,  Kenichi Mori

IPC分类号： H04K1/10

CPC分类号： H04L27/04 ,  H04L27/0008 ,  H04L27/206

摘要： A first signal generation section 11 generates a baseband modulation signal for an ASK modulation scheme from transmission data. A second signal generation section 12 generates a pair of baseband modulation signals for a non-ASK modulation scheme from transmission data. When performing non-ASK modulation, a switch 15 connects between an input terminal d and an output terminal and outputs the baseband modulation signals based on the non-ASK modulation. When performing ASK modulation such that the transmission power ratio of the ASK modulation scheme to the non-ASK modulation scheme is a factor of 1, a switch 14 connects between an input terminal b and an output terminal and the switch 15 connects between an input terminal c and the output terminal. When performing ASK modulation such that the transmission power ratio is a factor of 2, the switch 14 connects between an input terminal a and the output terminal and the switch 15 connects between the input terminal c and the output terminal.

摘要翻译： 第一信号生成部11从发送数据生成用于ASK调制方式的基带调制信号。 第二信号生成部分12从发送数据生成用于非ASK调制方案的一对基带调制信号。 当执行非ASK调制时，开关15在输入端子d和输出端子之间连接，并且基于非ASK调制输出基带调制信号。 当执行ASK调制使得ASK调制方案的发送功率比与非ASK调制方案的因数为1时，开关14在输入端子b和输出端子之间连接，并且开关15连接在输入端子 c和输出端子。 当执行ASK调制使得发送功率比为因子2时，开关14在输入端子a和输出端子之间连接，并且开关15连接在输入端子c和输出端子之间。

公开(公告)号：US20080118010A1

公开(公告)日：2008-05-22

申请号：US12003933

申请日：2008-01-03

申请人： Hideki Nakahara ,  Koichiro Tanaka ,  Kenichi Mori ,  Yoshio Urabe ,  Hitoshi Takai

发明人： Hideki Nakahara ,  Koichiro Tanaka ,  Kenichi Mori ,  Yoshio Urabe ,  Hitoshi Takai

IPC分类号： H04L27/06

CPC分类号： H04L7/041 ,  H04L7/0334 ,  H04L7/046 ,  H04L27/2332 ,  H04L2027/0036 ,  H04L2027/0067 ,  H04L2027/0095

摘要： A detected signal 111 contains a preamble portion which includes symbol alternations, followed by a unique word portion, and a data portion. Each time a symbol alternation is detected, a correction value calculation section 102 averages the phase shift in the detected signal 111 for a predetermined length, thereby calculating a correction value 115. The correction value determination section 103 stores a plurality of correction values 115 in a chronological order. When the unique word portion is detected, the correction value determination section 103 retains, as an effective correction value 118, a correction value which is arrived at by going back a predetermined number of correction values among the stored correction values. A phase rotation section 104 corrects the phase of the detected signal 111 by using an effective correction value 118 calculated by the correction value determination section 103.

公开(公告)号：US07336737B2

公开(公告)日：2008-02-26

申请号：US10690560

申请日：2003-10-23

申请人： Hideki Nakahara ,  Koichiro Tanaka ,  Kenichi Mori ,  Yoshio Urabe ,  Hitoshi Takai

发明人： Hideki Nakahara ,  Koichiro Tanaka ,  Kenichi Mori ,  Yoshio Urabe ,  Hitoshi Takai

IPC分类号： H04L27/06

CPC分类号： H04L7/041 ,  H04L7/0334 ,  H04L7/046 ,  H04L27/2332 ,  H04L2027/0036 ,  H04L2027/0067 ,  H04L2027/0095

摘要： A detected signal 111 contains a preamble portion which includes symbol alternations, followed by a unique word portion, and a data portion. Each time a symbol alternation is detected, a correction value calculation section 102 averages the phase shift in the detected signal 111 for a predetermined length, thereby calculating a correction value 115. The correction value determination section 103 stores a plurality of correction values 115 in a chronological order. When the unique word portion is detected, the correction value determination section 103 retains, as an effective correction value 118, a correction value which is arrived at by going back a predetermined number of correction values among the stored correction values. A phase rotation section 104 corrects the phase of the detected signal 111 by using an effective correction value 118 calculated by the correction value determination section 103.

摘要翻译： 检测信号111包含前导码部分，其包括符号替换，随后是唯一字部分和数据部分。 每当检测到符号交替时，校正值计算部分102将检测信号111中的相移平均预定长度，由此计算校正值115。 校正值确定部分103按时间顺序存储多个校正值115。 当检测到唯一字部分时，校正值确定部分103将存储的校正值中的预定数量的校正值返回到达到的校正值作为有效校正值118。 相位旋转部104通过使用由校正值确定部103计算出的有效校正值118来校正检测信号111的相位。

公开(公告)号：US20070297549A1

公开(公告)日：2007-12-27

申请号：US10591152

申请日：2005-03-18

申请人： Hideki Nakahara ,  Tomohiro Kimura ,  Hitoshi Takai ,  Kenichi Mori

发明人： Hideki Nakahara ,  Tomohiro Kimura ,  Hitoshi Takai ,  Kenichi Mori

IPC分类号： H04L7/00

CPC分类号： H04L7/0083 ,  H04L7/033

摘要： A clock recovery circuit capable of fast and accurate clock phase locking even in the presence of frequency shift and noise. The input signal includes, in order, a preamble with an alternating bit sequence pattern, a unique word and data. A detection unit detects zero crossings and measures the time interval therebetween. A 1-interval judgment unit judges whether an interval signal is within a predetermined range, and a 2-interval judgment unit sums two adjacent interval signals and judges whether the 2-interval signal is within a predetermined range. A control unit controls a zero-crossing signal based on the judgment result and outputs a valid zero-crossing signal if judged in the affirmative. A switching unit switches between outputting the zero-crossing signal and the valid zero-crossing signal as valid phase error information based on a frame reception signal input from a frame detection unit. A clock generation unit uses the valid phase error information in generating a symbol clock.

摘要翻译： 即使存在频移和噪声，时钟恢复电路也能够快速准确地进行时钟相位锁定。 输入信号按顺序包括具有交替位序列模式的前导码，唯一字和数据。 检测单元检测过零点并测量它们之间的时间间隔。 1间隔判断单元判断间隔信号是否在预定范围内，并且2间隔判断单元对两个相邻间隔信号求和，并判断2间隔信号是否在预定范围内。 控制单元根据判断结果控制过零信号，如果判断为肯定，则输出有效的过零信号。 切换单元基于从帧检测单元输入的帧接收信号，在输出过零信号和有效过零信号之间切换为有效的相位误差信息。 时钟生成单元在生成符号时钟时使用有效的相位误差信息。

公开(公告)号：US06181749B2

公开(公告)日：2001-01-30

申请号：US09182063

申请日：1998-10-29

申请人： Yoshio Urabe ,  Hitoshi Takai ,  Hidetoshi Yamasaki ,  Kenichi Mori

发明人： Yoshio Urabe ,  Hitoshi Takai ,  Hidetoshi Yamasaki ,  Kenichi Mori

IPC分类号： H04B708

CPC分类号： H01Q3/267 ,  H04B7/0817 ,  H04B7/0888 ,  H04L1/06

摘要： A demodulator 1 obtains demodulated data in a plurality of channels. Estimating portions 2a and 2b estimate and output the numbers of erroneous symbols and error locations thereof in the demodulated data. A data comparator 3 compares the demodulated data corresponding to the error locations with the demodulated data in the corresponding locations in other channels to determine whether the error location is correct, and it outputs a decision signal in response to the determination. A data selector 4 selects one of the demodulated data in the plurality of channels on the basis of the numbers of erroneous symbols and the decision signals and outputs the data as selected data. It is then possible to maintain the reliability of error detection even when a less redundant short error detecting code is used, and also to accurately select a channel of good quality even when the demodulated data in all channels contain the same extent of errors.

摘要翻译： 解调器1获得多个信道中的解调数据。 估计部分2a和2b估计并输出解调数据中的错误符号和错误位置的数目。 数据比较器3将对应于错误位置的解调数据与其他通道中的相应位置中的解调数据进行比较，以确定错误位置是否正确，并且响应于该确定而输出判定信号。 数据选择器4基于错误符号和判定信号的数量选择多个信道中的解调数据中的一个，并输出数据作为选择的数据。 即使当使用较少冗余的短错误检测码时也可以保持错误检测的可靠性，并且即使当所有信道中的解调数据包含相同的错误程度时，也可以准确地选择质量良好的信道。

公开(公告)号：US20050094745A1

公开(公告)日：2005-05-05

申请号：US10974723

申请日：2004-10-28

申请人： Kenji Miyanaga ,  Tomohiro Kimura ,  Kenichi Mori ,  Hitoshi Takai

发明人： Kenji Miyanaga ,  Tomohiro Kimura ,  Kenichi Mori ,  Hitoshi Takai

IPC分类号： H04L27/02 ,  H03M5/12 ,  H04L25/49 ,  H04L27/06 ,  H03D1/24

CPC分类号： H04L27/06 ,  H04L25/4904

摘要： A delay section delays a detected signal by less than one bit time in NRZ data. A subtraction section performs subtraction between a delayed signal and the detected signal, and outputs a resultant signal. A clock extraction section extracts, from crossing points of a subtracted signal, crossing points whose time interval is more than or equal to Tb-α and less than or equal to Tb+β (0

摘要翻译： 延迟部分在NRZ数据中将检测信号延迟小于一个位时间。 减法部分在延迟信号和检测信号之间进行减法，并输出结果信号。 时钟提取部从减法信号的交叉点提取时间间隔大于等于Tb-α且小于等于Tb +β的交叉点（0 <α≤Tb/8,0≤β <= Tb：Tb是NRZ数据中的一位时间），并且输出与提取的交叉点同步的同步信号。 时钟恢复部将时钟信号与同步信号的相位同步，并输出数据时钟信号。 确定部分根据数据时钟信号确定从减法部分输出的减法信号的极性，并将确定结果作为NRZ数据输出。

公开(公告)号：US07724856B2

公开(公告)日：2010-05-25

申请号：US10591152

申请日：2005-03-18

申请人： Hideki Nakahara ,  Tomohiro Kimura ,  Hitoshi Takai ,  Kenichi Mori

发明人： Hideki Nakahara ,  Tomohiro Kimura ,  Hitoshi Takai ,  Kenichi Mori

IPC分类号： H04L7/00

CPC分类号： H04L7/0083 ,  H04L7/033

摘要： A clock recovery circuit capable of fast and accurate clock phase locking even in the presence of frequency shift and noise. The input signal includes, in order, a preamble with an alternating bit sequence pattern, a unique word and data. A detection unit detects zero crossings and measures the time interval therebetween. A 1-interval judgment unit judges whether an interval signal is within a predetermined range, and a 2-interval judgment unit sums two adjacent interval signals and judges whether the 2-interval signal is within a predetermined range. A control unit controls a zero-crossing signal based on the judgment result and outputs a valid zero-crossing signal if judged in the affirmative. A switching unit switches between outputting the zero-crossing signal and the valid zero-crossing signal as valid phase error information based on a frame reception signal input from a frame detection unit. A clock generation unit uses the valid phase error information in generating a symbol clock.

摘要翻译： 即使存在频移和噪声，时钟恢复电路也能够快速准确地进行时钟相位锁定。 输入信号按顺序包括具有交替位序列模式的前导码，唯一字和数据。 检测单元检测过零点并测量它们之间的时间间隔。 1间隔判断单元判断间隔信号是否在预定范围内，并且2间隔判断单元对两个相邻间隔信号求和，并判断2间隔信号是否在预定范围内。 控制单元根据判断结果控制过零信号，如果判断为肯定，则输出有效的过零信号。 切换单元基于从帧检测单元输入的帧接收信号，在输出过零信号和有效过零信号之间切换为有效的相位误差信息。 时钟生成单元在生成符号时钟时使用有效的相位误差信息。