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    LOW-POWER CML-LESS TRANSMITTER ARCHITECTURE
    1.
    发明申请
    LOW-POWER CML-LESS TRANSMITTER ARCHITECTURE 有权
    低功耗CML-LESS发射机架构

    公开(公告)号：US20140269761A1

    公开(公告)日：2014-09-18

    申请号：US13835530

    申请日：2013-03-15

    申请人： Korea Advanced Institute of Science and Technology ,  TERASQUARE CO., LTD.

    发明人： Hyeon Min Bae ,  Tae Hun Yoon ,  Jin Ho Park ,  Tae Ho Kim

    IPC分类号： H04J3/04

    CPC分类号： H04J3/04 ,  H03K19/1737 ,  H04L25/0286

    摘要： Exemplary embodiments of the present invention relate to a low-power current mode logic (CML)-less transmitter architecture. A transmitter comprises a main multiplexer configured to generate a main data signal by multiplexing parallel main data signals retimed from a retimer for time margin between parallel input data signals and a multiphase clock signals from a clock distributor, a secondary multiplexer configured to generate a post data signal by multiplexing parallel post data signals retimed from the retimer, and a plurality of output drivers configured to generate a serial data signal by summing the main data signal and the post data signal.

    摘要翻译： 本发明的示例性实施例涉及低功率电流模式逻辑（CML）无发射机架构。 发射机包括：主多路复用器，被配置为通过将从重定时器重新定时的并行主数据信号复用在并行输入数据信号之间的时间间隔和来自时钟分配器的多相时钟信号之间产生主数据信号，辅复用器被配置为生成后数据 通过复原从重定时器重新定时的并行后数据信号的多个输出驱动器，以及配置成通过对主数据信号和后数据信号求和来产生串行数据信号的多个输出驱动器。

    Low-power highly-accurate passive multiphase clock generation scheme by using polyphase filters
    2.
    发明授权
    Low-power highly-accurate passive multiphase clock generation scheme by using polyphase filters 有权
    低功耗高精度无源多相时钟生成方案采用多相滤波器

    公开(公告)号：US08774336B2

    公开(公告)日：2014-07-08

    申请号：US13833407

    申请日：2013-03-15

    申请人： Korea Advanced Institute of Science and Technology ,  TeraSquare Co., Ltd.

    发明人： Hyeon Min Bae ,  Hyo Sup Won ,  Joon Yeong Lee ,  Jin Ho Park ,  Tae Ho Kim

    IPC分类号： H04L7/00 ,  H04L7/02

    CPC分类号： H04L7/00 ,  H03L7/0807 ,  H03L7/0814 ,  H04L7/0337

    摘要： Exemplary embodiments of the present invention relate to a low-power highly-accurate passive multiphase clock generation scheme by using polyphase filters. An exemplary embodiment of the present invention may be low power phase-rotator-based 25 GB/s CDR architecture in case that half-rate reference clock is provided. It may be suitable for multi-lane scheme and incorporate phase interpolator with improved phase accuracy to make Nyquist-sampling clock phase. To improve the phase accuracy, poly phase filter may be used for converting 4-phase to 8-phase and interpolate adjacent 45 degree different phases. The linearity of phase rotator may be improved by proposed harmonic rejection poly phase filter (HRPPF) using the characteristic of notch filter response.

    摘要翻译： 本发明的示例性实施例涉及通过使用多相滤波器的低功率高精度无源多相时钟生成方案。 在提供半速率参考时钟的情况下，本发明的示例性实施例可以是基于低功率相位旋转器的25GB / s CDR架构。 它可能适用于多通道方案，并且并入具有提高的相位精度的相位内插器，以使奈奎斯特采样时钟相位。 为了提高相位精度，多相滤波器可用于将4相转换为8相，并内插相邻的45度相位。 通过使用陷波滤波器响应的特性，提出的谐波抑制多相滤波器（HRPPF）可以改善相位旋转器的线性度。

    Adaptive optimum CDR bandwidth estimation by using a kalman gain extractor
    3.
    发明授权
    Adaptive optimum CDR bandwidth estimation by using a kalman gain extractor 有权
    通过使用卡尔曼增益提取器自适应优化CDR带宽估计

    公开(公告)号：US08938043B2

    公开(公告)日：2015-01-20

    申请号：US13833321

    申请日：2013-03-15

    申请人： Korea Advanced Institute of Science and Technology ,  TeraSquare Co., Ltd.

    发明人： Hyeon Min Bae ,  Joon Yeong Lee ,  Hyo Sup Won ,  Jong Hyeok Yoon ,  Jin Ho Park ,  Tae Ho Kim

    IPC分类号： H03D3/24 ,  H04L27/00 ,  H04L7/00 ,  H04L7/033

    CPC分类号： H04L7/007 ,  H04L7/0331

    摘要： Exemplary embodiments of the present invention relate to a clock and data recovery (CDR) apparatus with adaptive optimum CDR bandwidth estimation by using a Kalman gain extractor. The Kalman gain extractor includes an off chip digital processor which receives a phase update information from the CDR outputs an estimated optimum Kalman gain obtained by extracting the standard deviation of step sizes of the accumulation jitter from the power spectral density (PSD) of the phase update information, and a on chip digital loop filter consists of a cyclic accumulator which accumulates the phase detector's output, a gain multiplier and a phase interpolator (or DCO) controller. The off chip digital processor includes a storage register, a fast Fourier transform (FFT) processor and an optimum Kalman gain estimator. The storage register stores the phase update information, from which the FFT processor extracts the PSD of the absolute input jitter. The optimum Kalman gain estimator calculates the optimum gain from the PSD of the accumulation jitter. The off chip digital processor may further include a gain calibrator to compensate for the variations in the transition density.

    摘要翻译： 本发明的示例性实施例涉及通过使用卡尔曼增益提取器具有自适应最佳CDR带宽估计的时钟和数据恢复（CDR）装置。 卡尔曼增益提取器包括离线数字处理器，其接收来自CDR的相位更新信息，输出通过从相位更新的功率谱密度（PSD）提取积累抖动的步长的标准偏差而获得的估计的最佳卡尔曼增益 信息和片上数字环路滤波器由积累相位检测器输出的循环累加器，增益乘法器和相位内插器（或DCO）控制器组成。 片外数字处理器包括存储寄存器，快速傅里叶变换（FFT）处理器和最佳卡尔曼增益估计器。 存储寄存器存储相位更新信息，FFT处理器从该存储器提取绝对输入抖动的PSD。 最佳卡尔曼增益估计器从累积抖动的PSD计算最佳增益。 片外数字处理器还可以包括增益校准器，以补偿转换密度的变化。

    ADAPTIVE OPTIMUM CDR BANDWIDTH ESTIMATION BY USING A KALMAN GAIN EXTRACTOR
    4.
    发明申请
    ADAPTIVE OPTIMUM CDR BANDWIDTH ESTIMATION BY USING A KALMAN GAIN EXTRACTOR 有权
    使用卡曼增益提取器的自适应最佳CDR带宽估计

    公开(公告)号：US20130259178A1

    公开(公告)日：2013-10-03

    申请号：US13833321

    申请日：2013-03-15

    申请人： Korea Advanced Institute of Science and Technology ,  TERASQUARE CO., LTD.

    发明人： Hyeon Min Bae ,  Joon Young Lee ,  Hyo Sup Won ,  Jong Hyeok Yoon ,  Jin Ho Park ,  Tae Ho Kim

    IPC分类号： H04L7/00

    CPC分类号： H04L7/007 ,  H04L7/0331

    摘要： Exemplary embodiments of the present invention relate to a clock and data recovery (CDR) apparatus with adaptive optimum CDR bandwidth estimation by using a Kalman gain extractor. The Kalman gain extractor includes an off chip digital processor which receives a phase update information from the CDR outputs an estimated optimum Kalman gain obtained by extracting the standard deviation of step sizes of the accumulation jitter from the power spectral density (PSD) of the phase update information, and a on chip digital loop filter consists of a cyclic accumulator which accumulates the phase detector's output, a gain multiplier and a phase interpolator (or DCO) controller. The off chip digital processor includes a storage register, a fast Fourier transform (FFT) processor and an optimum Kalman gain estimator. The storage register stores the phase update information, from which the FFT processor extracts the PSD of the absolute input jitter. The optimum Kalman gain estimator calculates the optimum gain from the PSD of the accumulation jitter. The off chip digital processor may further include a gain calibrator to compensate for the variations in the transition density.

    摘要翻译： 本发明的示例性实施例涉及通过使用卡尔曼增益提取器具有自适应最佳CDR带宽估计的时钟和数据恢复（CDR）装置。 卡尔曼增益提取器包括离线数字处理器，其接收来自CDR的相位更新信息，输出通过从相位更新的功率谱密度（PSD）提取积累抖动的步长的标准偏差而获得的估计的最佳卡尔曼增益 信息和片上数字环路滤波器由积累相位检测器输出的循环累加器，增益乘法器和相位内插器（或DCO）控制器组成。 片外数字处理器包括存储寄存器，快速傅里叶变换（FFT）处理器和最佳卡尔曼增益估计器。 存储寄存器存储相位更新信息，FFT处理器从该存储器提取绝对输入抖动的PSD。 最佳卡尔曼增益估计器从累积抖动的PSD计算最佳增益。 片外数字处理器还可以包括增益校准器，以补偿转换密度的变化。

    LOW-POWER HIGHLY-ACCURATE PASSIVE MULTIPHASE CLOCK GENERATION SCHEME BY USING POLYPHASE FILTERS
    5.
    发明申请
    LOW-POWER HIGHLY-ACCURATE PASSIVE MULTIPHASE CLOCK GENERATION SCHEME BY USING POLYPHASE FILTERS 有权
    使用多相滤波器的低功耗高精度无源时钟产生方案

    公开(公告)号：US20130266103A1

    公开(公告)日：2013-10-10

    申请号：US13833407

    申请日：2013-03-15

    申请人： Korea Advanced Institute of Science and Technology ,  TERASQUARE CO., LTD.

    发明人： Hyeon Min Bae ,  Hyo Sup Won ,  Joon Young Lee ,  Jin Ho Park ,  Tae Ho Kim

    IPC分类号： H04L7/00

    CPC分类号： H04L7/00 ,  H03L7/0807 ,  H03L7/0814 ,  H04L7/0337

    摘要： Exemplary embodiments of the present invention relate to a low-power highly-accurate passive multiphase clock generation scheme by using polyphase filters. An exemplary embodiment of the present invention may be low power phase-rotator-based 25 GB/s CDR architecture in case that half-rate reference clock is provided. It may be suitable for multi-lane scheme and incorporate phase interpolator with improved phase accuracy to make Nyquist-sampling clock phase. To improve the phase accuracy, poly phase filter may be used for converting 4-phase to 8-phase and interpolate adjacent 45 degree different phases. The linearity of phase rotator may be improved by proposed harmonic rejection poly phase filter (HRPPF) using the characteristic of notch filter response.

    摘要翻译： 本发明的示例性实施例涉及通过使用多相滤波器的低功率高精度无源多相时钟生成方案。 在提供半速率参考时钟的情况下，本发明的示例性实施例可以是基于低功率相位旋转器的25GB / s CDR架构。 它可能适用于多通道方案，并且并入具有提高的相位精度的相位内插器，以使奈奎斯特采样时钟相位。 为了提高相位精度，多相滤波器可用于将4相转换为8相，并内插相邻的45度相位。 通过使用陷波滤波器响应的特性，提出的谐波抑制多相滤波器（HRPPF）可以改善相位旋转器的线性度。

    Low-power CML-less transmitter architecture
    6.
    发明授权
    Low-power CML-less transmitter architecture 有权
    低功耗无CML发射机架构

    公开(公告)号：US09419736B2

    公开(公告)日：2016-08-16

    申请号：US13835530

    申请日：2013-03-15

    申请人： Korea Advanced Institute of Science and Technology ,  TeraSquare Co., Ltd.

    发明人： Hyeon Min Bae ,  Tae Hun Yoon ,  Jin Ho Park ,  Tae Ho Kim

    IPC分类号： H04J3/04 ,  H03K19/173 ,  H04L25/02

    CPC分类号： H04J3/04 ,  H03K19/1737 ,  H04L25/0286

    摘要： Exemplary embodiments of the present invention relate to a low-power current mode logic (CML)-less transmitter architecture. A transmitter comprises a main multiplexer configured to generate a main data signal by multiplexing parallel main data signals retimed from a retimer for time margin between parallel input data signals and a multiphase clock signals from a clock distributor, a secondary multiplexer configured to generate a post data signal by multiplexing parallel post data signals retimed from the retimer, and a plurality of output drivers configured to generate a serial data signal by summing the main data signal and the post data signal.

    摘要翻译： 本发明的示例性实施例涉及低功率电流模式逻辑（CML）无发射机架构。 发射机包括：主多路复用器，被配置为通过将从重定时器重新定时的并行主数据信号复用在并行输入数据信号之间的时间间隔和来自时钟分配器的多相时钟信号之间产生主数据信号，辅复用器被配置为生成后数据 通过复原从重定时器重新定时的并行后数据信号的多个输出驱动器，以及被配置为通过对主数据信号和后数据信号求和来产生串行数据信号的多个输出驱动器。

    Low-power and all-digital phase interpolator-based clock and data recovery architecture
    8.
    发明授权
    Low-power and all-digital phase interpolator-based clock and data recovery architecture 有权
    基于低功耗和全数字相位插值器的时钟和数据恢复架构

    公开(公告)号：US09166605B2

    公开(公告)日：2015-10-20

    申请号：US13846688

    申请日：2013-03-18

    申请人： Korea Advanced Institute of Science and Technology

    发明人： Hyeon Min Bae ,  Tae Hun Yoon ,  Joon Yeong Lee

    IPC分类号： H03L7/00 ,  H03L7/081 ,  H04J3/06 ,  H03L7/07 ,  H03L7/099

    CPC分类号： H03L7/081 ,  H03L7/07 ,  H03L7/0814 ,  H03L7/0998 ,  H04J3/06

    摘要： The proposed invention is about an improved method for serial-in and serial-out transceiver applications. The proposed system includes a dual loop phase locked loop (PLL) architecture having a PLL and a phase rotator (PR)-based delay locked loop (DLL). An advantage of this architecture is that a single PLL offers decoupled bandwidths; a wide jitter-tolerance (JTOL) bandwidth for receiving data and a narrow jitter transfer (JTRAN) bandwidth for the data transmission. Thus, the amount of jitter at the output can be substantially reduced relative to the input while offering sufficient jitter tracking bandwidth. Also, this architecture is suitable for low-power applications since a phase shifter in the data path, which is one of the most power-hungry blocks in conventional DPLL designs, is not required.

    摘要翻译： 所提出的发明是关于串行和串行收发器应用的改进方法。 所提出的系统包括具有PLL和基于相位旋转器（PR）的延迟锁定环（DLL）的双环路锁相环（PLL）架构。 该架构的优点是单个PLL提供去耦带宽; 用于接收数据的宽抖动容限（JTOL）带宽和用于数据传输的窄抖动传输（JTRAN）带宽。 因此，在提供足够的抖动跟踪带宽的同时，输出端的抖动量可以相对于输入显着减小。 此外，该架构适用于低功耗应用，因为数据路径中的移相器是传统DPLL设计中功耗最大的块之一。