公开(公告)号：US20090014841A1

公开(公告)日：2009-01-15

申请号：US12169270

申请日：2008-07-08

申请人： Kosuke YANAGIDAIRA ,  Takuya Futatsuyama ,  Toshiya Kotani

发明人： Kosuke YANAGIDAIRA ,  Takuya Futatsuyama ,  Toshiya Kotani

IPC分类号： H01L29/06 ,  G11C5/02

CPC分类号： G11C5/02 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11526

摘要： A first region having a first pattern which includes a first minimum dimension, a second region having a second pattern which includes a second minimum dimension larger the first minimum dimension, the second region being arranged adjacent to the first region, wherein a boundary between the first region and the second region is sectioned by a width which is twice of more of a minimum dimension which exists in an adjacent region.

摘要翻译： 具有包括第一最小尺寸的第一图案的第一区域，具有第二图案的第二区域，所述第二图案包括具有大于所述第一最小尺寸的第二最小尺寸，所述第二区域布置成与所述第一区域相邻，其中所述第一图案 区域，并且第二区域被存在于相邻区域中的最小尺寸的两倍以上的宽度分割。

公开(公告)号：US20090155990A1

公开(公告)日：2009-06-18

申请号：US12332788

申请日：2008-12-11

申请人： Kosuke YANAGIDAIRA ,  Chikaaki KODAMA

发明人： Kosuke YANAGIDAIRA ,  Chikaaki KODAMA

IPC分类号： H01L21/768 ,  G06F17/50

CPC分类号： H01L23/528 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/76816 ,  H01L21/76877 ,  H01L23/48 ,  H01L23/522 ,  H01L27/0207 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11529 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for manufacturing a semiconductor device of one embodiment of the present invention includes: forming an insulation layer to be processed over a substrate; forming a first sacrificial layer in a first area over the substrate, the first sacrificial layer being patterned to form in the first area a functioning wiring connected to an element; forming a second sacrificial layer in a second area over the substrate, the second sacrificial layer being patterned to form in the second area a dummy wiring; forming a third sacrificial layer at a side wall of the first sacrificial layer and forming a fourth sacrificial layer at a side wall of the second sacrificial layer, the third sacrificial layer and the fourth sacrificial layer being separated; forming a concavity by etching the insulation layer to be processed using the third sacrificial layer and the fourth sacrificial layer as a mask; and filling a conductive material in the concavity.

摘要翻译： 本发明的一个实施例的半导体器件的制造方法包括：在衬底上形成待加工的绝缘层; 在所述衬底上的第一区域中形成第一牺牲层，所述第一牺牲层被图案化以在所述第一区域中形成连接到元件的功能线; 在所述衬底上的第二区域中形成第二牺牲层，所述第二牺牲层被图案化以在所述第二区域中形成虚拟布线; 在所述第一牺牲层的侧壁处形成第三牺牲层，并在所述第二牺牲层的侧壁处形成第四牺牲层，所述第三牺牲层和所述第四牺牲层被分离; 通过使用第三牺牲层和第四牺牲层作为掩模蚀刻待处理的绝缘层来形成凹部; 并在凹部中填充导电材料。

公开(公告)号：US20100034025A1

公开(公告)日：2010-02-11

申请号：US12507366

申请日：2009-07-22

申请人： Kosuke YANAGIDAIRA ,  Toshihiro Suzuki ,  Naoya Tokiwa

发明人： Kosuke YANAGIDAIRA ,  Toshihiro Suzuki ,  Naoya Tokiwa

IPC分类号： G11C16/04 ,  G11C7/00 ,  G11C29/00

CPC分类号： G11C16/349

摘要： There is provided a non-volatile memory having electrically rewritable non-volatile memory cells arranged therein. A controller controls operation at the non-volatile memory. The non-volatile memory comprises a status output section configured to output status information indicating a status of read operation, write operation or erase operation in the non-volatile memory cell. The controller comprises a control signal generating section configured to output a control signal for a certain operation in the non-volatile memory, and a control signal switching section configured to instruct the control signal generating section to switch the control signal based on the status information.

摘要翻译： 提供了一种其中布置有电可重写非易失性存储单元的非易失性存储器。 控制器控制非易失性存储器的操作。 非易失性存储器包括状态输出部分，被配置为在非易失性存储器单元中输出指示读取操作，写入操作或擦除操作的状态的状态信息。 所述控制器包括：控制信号生成部，被配置为输出用于所述非易失性存储器中的某个操作的控制信号;以及控制信号切换部，被配置为指示所述控制信号生成部基于所述状态信息来切换所述控制信号。

公开(公告)号：US20130164934A1

公开(公告)日：2013-06-27

申请号：US13665803

申请日：2012-10-31

申请人： Kosuke YANAGIDAIRA ,  Chikaaki KODAMA

发明人： Kosuke YANAGIDAIRA ,  Chikaaki KODAMA

IPC分类号： H01L21/768

CPC分类号： H01L23/528 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/76816 ,  H01L21/76877 ,  H01L23/48 ,  H01L23/522 ,  H01L27/0207 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11529 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for manufacturing a semiconductor device of one embodiment of the present invention includes: forming an insulation layer to be processed over a substrate; forming a first sacrificial layer in a first area over the substrate, the first sacrificial layer being patterned to form in the first area a functioning wiring connected to an element; forming a second sacrificial layer in a second area over the substrate, the second sacrificial layer being patterned to form in the second area a dummy wiring; forming a third sacrificial layer at a side wall of the first sacrificial layer and forming a fourth sacrificial layer at a side wall of the second sacrificial layer, the third sacrificial layer and the fourth sacrificial layer being separated; forming a concavity by etching the insulation layer to be processed using the third sacrificial layer and the fourth sacrificial layer as a mask; and filling a conductive material in the concavity.

公开(公告)号：US20090303790A1

公开(公告)日：2009-12-10

申请号：US12478172

申请日：2009-06-04

申请人： Tomofumi FUJIMURA ,  Kosuke YANAGIDAIRA

发明人： Tomofumi FUJIMURA ,  Kosuke YANAGIDAIRA

IPC分类号： G11C16/04

CPC分类号： G11C16/16 ,  G11C16/3409 ,  G11C16/344 ,  G11C16/3445

摘要： The present invention provides a semiconductor memory device that can minimize the widening of the threshold voltage distribution of cell transistors during a data erasing operation. The semiconductor memory device includes: a memory cell unit that is formed with nonvolatile memory cells connected in series, is divided into at least two groups each including one or more of the nonvolatile memory cells, and has one end connected to a source line and the other end connected to a bit line, word lines being connected to the gates of the nonvolatile memory cells, the voltages of the word lines being controlled to store data from the bit line or output stored data onto the bit line; and a voltage applying circuit that applies voltages to the word lines of the nonvolatile memory cells, applying a first voltage to the word lines of the nonvolatile memory cells of the group located closer to the bit line, and applying a second voltage to the word lines of the nonvolatile memory cells of the group located closer to the source line, with respect to the two adjacent groups of the memory cell unit, when a data erasing operation is performed to erase data stored in the nonvolatile memory cells forming the memory cell unit, the second voltage being higher than the first voltage.

摘要翻译： 本发明提供一种半导体存储器件，其能够在数据擦除操作期间最小化单元晶体管的阈值电压分布的加宽。 半导体存储器件包括：形成有串联连接的非易失性存储单元的存储单元单元，被分成至少两组，每组包括一个或多个非易失性存储单元，并且其一端连接到源极线，并且 另一端连接到位线，字线连接到非易失性存储单元的栅极，字线的电压被控制以存储来自位线的数据或将存储的数据输出到位线; 以及电压施加电路，对所述非易失性存储单元的字线施加电压，向位于所述位线附近的所述组的所述非易失性存储单元的字线施加第一电压，并向所述字线施加第二电压 相对于存储单元单元的两个相邻组而言，位于更靠近源极线的组的非易失性存储单元当执行数据擦除操作以擦除存储在形成存储单元单元的非易失性存储单元中的数据时， 第二电压高于第一电压。

公开(公告)号：US20090256265A1

公开(公告)日：2009-10-15

申请号：US12407613

申请日：2009-03-19

申请人： Kazuyuki MASUKAWA ,  Koji HASHIMOTO ,  Hidefumi MUKAI ,  Kosuke YANAGIDAIRA

发明人： Kazuyuki MASUKAWA ,  Koji HASHIMOTO ,  Hidefumi MUKAI ,  Kosuke YANAGIDAIRA

IPC分类号： H01L23/535

CPC分类号： H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor integrated circuit device includes a plurality of contact layers located between two lines running in parallel in a first direction. Each of the contact layers has a structure in which an upper contact and a lower contact are coupled together. The plurality of contact layers are arranged zigzag along the first direction, and coupling portions of the upper contact and the lower contact are displaced from the center of the upper contact in a second direction perpendicular to the first direction.

摘要翻译： 半导体集成电路器件包括位于沿第一方向平行运行的两条线之间的多个接触层。 每个接触层具有其中上触点和下触点耦合在一起的结构。 所述多个接触层沿着所述第一方向被锯齿形地设置，并且所述上触点和所述下触点的耦合部分在垂直于所述第一方向的第二方向上从所述上接触件的中心位移。