公开(公告)号：US20050017274A1

公开(公告)日：2005-01-27

申请号：US10920389

申请日：2004-08-18

申请人： Kozo Watanabe ,  Atsushi Ogishima ,  Masahiro Moniwa ,  Syunichi Hashimoto ,  Masayuki Kojima ,  Kiyonori Ohyu ,  Kenichi Kuroda ,  Nozomu Matsuda

发明人： Kozo Watanabe ,  Atsushi Ogishima ,  Masahiro Moniwa ,  Syunichi Hashimoto ,  Masayuki Kojima ,  Kiyonori Ohyu ,  Kenichi Kuroda ,  Nozomu Matsuda

IPC分类号： H01L21/8242 ,  H01L27/105 ,  H01L27/108 ,  H01L29/76

CPC分类号： H01L27/10852 ,  H01L27/105 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/10873 ,  H01L27/10888 ,  H01L27/10894 ,  Y10S257/90

摘要： A technology for a semiconductor integrated circuitry allows each of the DRAM memory cells to be divided finely so as to be more highly integrated and operate faster. In a method of manufacturing such a semiconductor integrated circuit, at first, gate electrodes 7 are formed via a gate insulating film 6 on the main surface of a semiconductor substrate 1, and on side surfaces of each of the gate electrodes there is formed a first side wall spacer 14 composed of silicon nitride and a second side wall spacer 15 composed of silicon oxide. Then, in the selecting MISFET Qs in the DRAM memory cell area there are opened connecting holes 19 and 21 in a self-matching manner with respect to the first side wall spacers 14 and connecting portion is formed connecting a conductor 20 to a bit line BL. In addition, in the N channel MISFETs Qn1 and Qn2, and in the P channel MISFET Qp1 in areas other than the DRAM memory cell area, high density N-type semiconductor areas 16 and 16b are formed, as well as a high density P-type semiconductor area 17 is formed in a self-matching manner with respect to the second side wall spacers 15.

摘要翻译： 用于半导体集成电路的技术允许每个DRAM存储单元被细分，以便更高度地集成并且操作更快。 在制造这样的半导体集成电路的方法中，首先，在半导体衬底1的主表面上经由栅极绝缘膜6形成栅电极7，并且在每个栅电极的侧表面上形成第一 由氮化硅构成的侧壁隔板14和由氧化硅构成的第二侧壁间隔物15。 然后，在DRAM存储单元区域中的选择MISFET Qs中，相对于第一侧壁间隔件14以自匹配的方式打开连接孔19和21，并且连接部分形成为将导体20连接到位线BL 。 此外，在N沟道MISFET Qn1和Qn2以及在DRAM存储单元区域以外的区域中的P沟道MISFET Qp1中，形成高密度N型半导体区域16和16b以及高密度P- 型半导体区域17相对于第二侧壁间隔件15以自匹配的方式形成。

公开(公告)号：US06800888B2

公开(公告)日：2004-10-05

申请号：US10759238

申请日：2004-01-20

申请人： Kozo Watanabe ,  Atsushi Ogishima ,  Masahiro Moniwa ,  Syunichi Hashimoto ,  Masayuki Kojima ,  Kiyonori Ohyu ,  Kenichi Kuroda ,  Nozomu Matsuda

发明人： Kozo Watanabe ,  Atsushi Ogishima ,  Masahiro Moniwa ,  Syunichi Hashimoto ,  Masayuki Kojima ,  Kiyonori Ohyu ,  Kenichi Kuroda ,  Nozomu Matsuda

IPC分类号： H01L2976

CPC分类号： H01L27/10852 ,  H01L27/105 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/10873 ,  H01L27/10888 ,  H01L27/10894 ,  Y10S257/90

摘要： A technology for a semiconductor integrated circuitry allows each of the DRAM memory cells to be divided finely so as to be more highly integrated and operate faster. In a method of manufacturing such a semiconductor integrated circuit, at first, gate electrodes 7 are formed via a gate insulating film 6 on the main surface of a semiconductor substrate 1, and on side surfaces of each of the gate electrodes there is formed a first side wall spacer 14 composed of silicon nitride and a second side wall spacer 15 composed of silicon oxide. Then, in the selecting MISFET Qs in the DRAM memory cell area there are opened connecting holes 19 and 21 in a self-matching manner with respect to the first side wall spacers 14 and connecting portion is formed connecting a conductor 20 to a bit line BL. In addition, in the N channel MISFETs Qn1 and Qn2, and in the P channel MISFET Qp1 in areas other than the DRAM memory cell area, high density N-type semiconductor areas 16 and 16b are formed, as well as a high density P-type semiconductor area 17 is formed in a self-matching manner with respect to the second side wall spacers 15.

公开(公告)号：US06503794B1

公开(公告)日：2003-01-07

申请号：US09381345

申请日：1999-09-20

申请人： Kozo Watanabe ,  Atsushi Ogishima ,  Masahiro Moniwa ,  Syunichi Hashimoto ,  Masayuki Kojima ,  Kiyonori Ohyu ,  Kenichi Kuroda ,  Nozomu Matsuda

发明人： Kozo Watanabe ,  Atsushi Ogishima ,  Masahiro Moniwa ,  Syunichi Hashimoto ,  Masayuki Kojima ,  Kiyonori Ohyu ,  Kenichi Kuroda ,  Nozomu Matsuda

IPC分类号： H01L218242

CPC分类号： H01L27/10852 ,  H01L27/105 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/10873 ,  H01L27/10888 ,  H01L27/10894 ,  Y10S257/90

摘要： It is an object of the present invention to provide a technology of a semiconductor integrated circuitry that allows each of the DRAM memory cells to be divided finely so as to be more highly integrated and operated faster. In a method for manufacturing such a semiconductor integrated circuitry of the present invention, at first, gate electrodes 7 are formed via a gate insulating film 6 on the main surface of a semiconductor substrate 1, and on side surfaces of each of the gate electrodes is formed the first side wall spacer 14 composed of silicon nitride and the second side wall spacer 15 composed of silicon oxide. Then, in the selecting MISFET Qs in the DRAM memory cell area are opened connecting holes 19 and 21 in a self-matching manner with respect to the first side wall spacers 14 and are formed connecting portion connecting a conductor 20 to a bit line BL. In addition, in the N channel MISFETs Qn1 and Qn2, and in the P channel MISFET Qp1 in areas other than the DRAM memory cell area are formed high density N-type semiconductor areas 16 and 16b, as well as a high density P-type semiconductor area 17 in a self-matching manner with respect to the second side wall spacers 15.

摘要翻译： 本发明的一个目的是提供一种半导体集成电路的技术，该技术允许每个DRAM存储器单元被细分，以便更高集成度和更快地运行。 在本发明的这种半导体集成电路的制造方法中，首先，通过半导体基板1的主面上的栅极绝缘膜6形成栅电极7，在各栅极电极的侧面 形成由氮化硅构成的第一侧壁隔离物14和由氧化硅构成的第二侧壁隔离物15。 然后，在DRAM存储单元区域中的选择MISFET Qs中，以相对于第一侧壁隔板14的自匹配方式打开连接孔19和21，并且形成将导体20连接到位线BL的连接部分。 此外，在N沟道MISFET Qn1和Qn2中以及在DRAM存储单元区域以外的区域中的P沟道MISFET Qp1中形成高密度N型半导体区域16和16b，以及高密度P型 半导体区域17相对于第二侧壁间隔件15以自匹配的方式。

公开(公告)号：US07081649B2

公开(公告)日：2006-07-25

申请号：US10920389

申请日：2004-08-18

申请人： Kozo Watanabe ,  Atsushi Ogishima ,  Masahiro Moniwa ,  Syunichi Hashimoto ,  Masayuki Kojima ,  Kiyonori Ohyu ,  Kenichi Kuroda ,  Nozomu Matsuda

发明人： Kozo Watanabe ,  Atsushi Ogishima ,  Masahiro Moniwa ,  Syunichi Hashimoto ,  Masayuki Kojima ,  Kiyonori Ohyu ,  Kenichi Kuroda ,  Nozomu Matsuda

IPC分类号： H01L29/76

CPC分类号： H01L27/10852 ,  H01L27/105 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/10873 ,  H01L27/10888 ,  H01L27/10894 ,  Y10S257/90

摘要： A technology for a semiconductor integrated circuitry allows each of the DRAM memory cells to be divided finely so as to be more highly integrated and operate faster. In a method of manufacturing such a semiconductor integrated circuit, at first, gate electrodes 7 are formed via a gate insulating film 6 on the main surface of a semiconductor substrate 1, and on side surfaces of each of the gate electrodes there is formed a first side wall spacer 14 composed of silicon nitride and a second side wall spacer 15 composed of silicon oxide. Then, in the selecting MISFET Qs in the DRAM memory cell area there are opened connecting holes 19 and 21 in a self-matching manner with respect to the first side wall spacers 14 and connecting portion is formed connecting a conductor 20 to a bit line BL. In addition, in the N channel MISFETs Qn1 and Qn2, and in the P channel MISFET Qp1 in areas other than the DRAM memory cell area, high density N-type semiconductor areas 16 and 16b are formed, as well as a high density P-type semiconductor area 17 is formed in a self-matching manner with respect to the second side wall spacers 15.

摘要翻译： 用于半导体集成电路的技术允许每个DRAM存储单元被细分，以便更高度地集成并且操作更快。 在制造这样的半导体集成电路的方法中，首先，在半导体衬底1的主表面上经由栅极绝缘膜6形成栅电极7，并且在每个栅电极的侧表面上形成第一 由氮化硅构成的侧壁隔板14和由氧化硅构成的第二侧壁间隔物15。 然后，在DRAM存储单元区域中的选择MISFET Qs中，相对于第一侧壁间隔件14以自匹配的方式打开连接孔19和21，并且连接部分形成为将导体20连接到位线BL 。 此外，在N沟道MISFET Qn 1和Q n 2以及在DRAM存储单元区域以外的区域中的P沟道MISFET Qp 1中，形成高密度N型半导体区域16和16b，以及 高密度P型半导体区域17相对于第二侧壁间隔件15以自匹配的方式形成。

公开(公告)号：US06743673B2

公开(公告)日：2004-06-01

申请号：US10145810

申请日：2002-05-16

申请人： Kozo Watanabe ,  Atsushi Ogishima ,  Masahiro Moniwa ,  Syunichi Hashimoto ,  Masayuki Kojima ,  Kiyonori Ohyu ,  Kenichi Kuroda ,  Nozomu Matsuda

发明人： Kozo Watanabe ,  Atsushi Ogishima ,  Masahiro Moniwa ,  Syunichi Hashimoto ,  Masayuki Kojima ,  Kiyonori Ohyu ,  Kenichi Kuroda ,  Nozomu Matsuda

IPC分类号： H01L218242

CPC分类号： H01L27/10852 ,  H01L27/105 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/10873 ,  H01L27/10888 ,  H01L27/10894 ,  Y10S257/90

摘要： A technology for a semiconductor integrated circuitry allows each of the DRAM memory cells to be divided finely so as to be more highly integrated and operate faster. In a method of manufacturing such a semiconductor integrated circuit, at first, gate electrodes 7 are formed via a gate insulating film 6 on the main surface of a semiconductor substrate 1, and on side surfaces of each of the gate electrodes there is formed a first side wall spacer 14 composed of silicon nitride and a second side wall spacer 15 composed of silicon oxide. Then, in the selecting MISFET Qs in the DRAM memory cell area there are opened connecting holes 19 and 21 in a self-matching manner with respect to the first side wall spacers 14 and connecting portion is formed connecting a conductor 20 to a bit line BL. In addition, in the N channel MISFETs Qn1 and Qn2, and in the P channel MISFET Qp1 in areas other than the DRAM memory cell area, high density N-type semiconductor areas 16 and 16b are formed, as well as a high density P-type semiconductor area 17 is formed in a self-matching manner with respect to the second side wall spacers 15.

摘要翻译： 用于半导体集成电路的技术允许每个DRAM存储单元被细分，以便更高度地集成并且操作更快。 在制造这样的半导体集成电路的方法中，首先，在半导体衬底1的主表面上经由栅极绝缘膜6形成栅电极7，并且在每个栅电极的侧表面上形成第一 由氮化硅构成的侧壁隔板14和由氧化硅构成的第二侧壁间隔物15。 然后，在DRAM存储单元区域中的选择MISFET Qs中，相对于第一侧壁间隔件14以自匹配的方式打开连接孔19和21，并且连接部分形成为将导体20连接到位线BL 。 此外，在N沟道MISFET Qn1和Qn2以及在DRAM存储单元区域以外的区域中的P沟道MISFET Qp1中，形成高密度N型半导体区域16和16b以及高密度P- 型半导体区域17相对于第二侧壁间隔件15以自匹配的方式形成。

公开(公告)号：US3971615A

公开(公告)日：1976-07-27

申请号：US564708

申请日：1975-04-03

申请人： Syunichi Hashimoto

发明人： Syunichi Hashimoto

IPC分类号： H01R4/24 ,  H01R9/08

CPC分类号： H01R4/2404

摘要： A connector for forming a series electrical connection between opposing ends of a pair of insulation-covered wires comprises a lower body portion having a longitudinal groove and a pair of upper body portions connected to and superimposable upon the lower body portion. Each of the upper body portions has a longitudinal groove for receiving and maintaining one wire end within the groove in the lower body portion. Each of the upper and lower body portions contain formations for receiving a conductive connecting piece having a pair of opposed blade portions for piercing the insulation to contact each wire end for forming a series connection. Opposing ends of the groove in the lower body portion and the outer ends of the groove in each upper body portion are formed with a thin yieldable wall for resiliently holding each wire end. Complementary means are attached to each body portion for mechanically fastening each upper body portion to the lower body portion to positively maintain proper electrical connection between the opposed wire ends.

摘要翻译： 用于在一对绝缘包线之间的相对端之间形成串联电连接的连接器包括具有纵向槽的下主体部分和连接到下主体部分并且可重叠在下主体部分上的一对上主体部分。 每个上体部分具有用于在下主体部分中的槽内容纳和保持一个丝线端部的纵向凹槽。 上部和下部主体部分都包含用于接收导电连接件的结构，该导电连接件具有一对相对的刀片部分，用于刺穿绝缘体以接触每个电线端部以形成串联连接。 在每个上部主体部分的下部主体部分中的槽的相对端和槽的外端形成有用于弹性地保持每个线端的薄的可收缩壁。 互补装置附接到每个主体部分，用于将每个上部主体部分机械地固定到下主体部分，以便在相对的导线端部之间积极地保持适当的电连接。

公开(公告)号：US3971616A

公开(公告)日：1976-07-27

申请号：US575660

申请日：1975-05-08

申请人： Syunichi Hashimoto

发明人： Syunichi Hashimoto

IPC分类号： H01R4/24 ,  H01R13/38

CPC分类号： H01R4/2404

摘要： An electrical parallel connector comprising an integral unitary structure formed of electrical insulation hard synthetic resin and including a rectangular first connector member and a rectangular second connector member integrally connected to said first connector member by means of flexible connection strips, said first connector member having a plurality of parallel grooves extending by a substantial portion of the length of the connector member in one major surface thereof and terminating short of the opposite ends of the connector member to provide end walls which define the opposite ends of said grooves, projections on the opposite sides of said connector member for engaging the opposite sides of the second connector member, recesses in the opposite side edges of said connector member positioned adjacent to and inwardly of said projections and extending into the bottom of the adjacent groove at right angles to the groove and an intermediate recess positioned between said first mentioned recesses and extending into the bottoms of the adjacent grooves; and said second connector member having a plurality of parallel grooves extending by a substantial portion of the length of the connector member in one major surface of the connector member and terminating short of the opposite ends of the connector member to provide end walls which define the opposite ends of the grooves, the number of said grooves in the second connector member corresponding to that of said grooves in the first connector member, projections at the opposite side edges of the second connector member projecting outwardly of the major surface for engaging in said recesses in the opposite side edges of said first connector member and a recess extending between said side edge projections of the second connector member and intersecting said grooves in the second connector member at right angles thereto; further including an electrically conductive connecting blade engaging in said recesses in the first and second connector members and covered wires received in said grooves in the first and second grooves and held in position by said blade.