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    Apparatus and methods for detection of systematic defects
    1.
    发明授权
    Apparatus and methods for detection of systematic defects 有权
    用于检测系统缺陷的装置和方法

    公开(公告)号：US07280945B1

    公开(公告)日：2007-10-09

    申请号：US10187567

    申请日：2002-07-01

    申请人： Kurt H. Weiner ,  Gaurav Verma ,  Indranil De

    发明人： Kurt H. Weiner ,  Gaurav Verma ,  Indranil De

    IPC分类号： G06F17/10 ,  G06F17/50

    CPC分类号： G01R31/318364

    摘要： Disclosed are mechanisms are provided for determining whether a particular integrated circuit (IC) pattern is susceptible to systematic failure, e.g., due to process fluctuations. In one embodiment, final resist patterns for such IC pattern are simulated using a sparse type simulator under various process settings. The sparse type simulator uses a model (e.g., a variable threshold resist model) for a particular photolithography process in which the IC pattern is to be fabricated. The model is generated from measurements taken from a plurality of simulated structures output from a rigorous type simulator. The simulated final resist patterns may then be analyzed to determine whether the corresponding IC pattern is susceptible to systematic failure. After an IC pattern which is susceptible to systematic failure has been found, a test structure may be fabricated from a plurality of IC patterns or cells. The cells of the test structure are arranged to have a particular pattern of voltage potential or brightness levels during a voltage contrast inspection. Mechanisms for quickly inspecting such test structures to thereby predict systematic yield of a product device containing patterns similar to the test structure cells are also disclosed.

    摘要翻译： 公开了提供用于确定特定集成电路（IC）模式是否易于系统故障（例如由于过程波动）的机制。 在一个实施例中，使用在各种处理设置下的稀疏型模拟器来模拟这种IC图案的最终抗蚀剂图案。 稀疏型模拟器对于要制造IC图案的特定光刻工艺使用模型（例如，可变阈值抗蚀剂模型）。 该模型是从从严格型模拟器输出的多个模拟结构中获得的测量产生的。 然后可以分析模拟的最终抗蚀剂图案，以确定相应的IC图案是否易于发生系统故障。 在已经发现容易发生系统故障的IC图案之后，可以从多个IC图案或单元制造测试结构。 测试结构的单元被布置成在电压对比度检查期间具有电压电位或亮度水平的特定图案。 还公开了用于快速检查这种测试结构从而预测包含类似于测试结构单元的图案的产品设备的系统产量的机制。

    Apparatus and methods for predicting multiple product chip yields through critical area matching
    5.
    发明授权
    Apparatus and methods for predicting multiple product chip yields through critical area matching 有权
    通过临界区域匹配预测多个产品芯片产量的装置和方法

    公开(公告)号：US06732002B1

    公开(公告)日：2004-05-04

    申请号：US09991188

    申请日：2001-11-14

    申请人： Kurt H. Weiner ,  Gaurav Verma

    发明人： Kurt H. Weiner ,  Gaurav Verma

    IPC分类号： G06F1900

    CPC分类号： H01L22/34 ,  G01R31/2884 ,  G01R31/2894 ,  G01R31/307

    摘要： Disclosed are methods and apparatus for sampling defects. A test chip having a plurality of test structures is provided that is designed so that defect sampling may be customized to obtain different critical areas from the test chip. Each test structure is conceptually divided into a plurality of unit cells (e.g., a pair of grounded and floating conductive lines). The defects of a percentage of unit cells may then be sampled for each test structure to conceptually form a sub test structure that has a different size than the original test structure. The percentage of unit cells that are sampled for each test structure is chosen so as to achieve a specific critical area curve. The defects from each sampled set of unit cells may then combined to determine yield for a product chip having the same specific critical area curve. These defect sampling techniques are customizable for different product chips having different critical areas to thereby predict product yield for such product chips using the same test chip. In general terms, a first set of unit cells may be sampled from the test structures to predict yield for a product chip having a first critical area, and a second different set of unit cells may be sampled to predict yield for a product chip having a second critical area. The test structures may have different characteristics, such a different line widths and spacing, that are sampled for defects to provide different critical area curves. In other specific implementations, one or more test structure may have one or more attributes that affect systematic yield, as compared to random attributes which affect random yield.

    摘要翻译： 公开了用于采样缺陷的方法和装置。 提供了具有多个测试结构的测试芯片，其被设计成使得可以定制缺陷采样以从测试芯片获得不同的关键区域。 每个测试结构在概念上被划分为多个单位单元（例如，一对接地和浮动导电线）。 然后可以对每个测试结构采样单位单元百分比的缺陷，以概念地形成具有与原始测试结构不同的尺寸的子测试结构。 选择为每个测试结构采样的单位单元的百分比，以便达到特定的临界面积曲线。 然后可以组合来自每个采样的单位单元组的缺陷以确定具有相同特定临界面积曲线的产品芯片的产量。 这些缺陷采样技术可针对具有不同关键区域的不同产品芯片进行定制，从而通过使用相同的测试芯片预测这种产品芯片的产品产量。 一般来说，可以从测试结构中采样第一组单位单元以预测具有第一临界区域的产品芯片的产量，并且可以采样第二不同组的单位单元以预测具有 第二关键领域。 测试结构可以具有不同的特征，例如不同的线宽和间隔，其被采样用于缺陷以提供不同的临界面曲线。 在其他具体实现中，与影响随机产出的随机属性相比，一个或多个测试结构可以具有影响系统产量的一个或多个属性。

    Apparatus and methods for fast chemical electrodeposition for fabrication of solar cells
    6.
    发明授权
    Apparatus and methods for fast chemical electrodeposition for fabrication of solar cells 有权
    快速化学电沉积制造太阳能电池的装置和方法

    公开(公告)号：US08343327B2

    公开(公告)日：2013-01-01

    申请号：US12787330

    申请日：2010-05-25

    申请人： Kurt H. Weiner ,  Gaurav Verma

    发明人： Kurt H. Weiner ,  Gaurav Verma

    IPC分类号： C25D5/10 ,  C25D5/00 ,  C25D17/00

    CPC分类号： C25D5/022 ,  C25D5/08 ,  C25D17/001 ,  C25D17/005 ,  C25D17/12

    摘要： The invention relates generally to electrodeposition apparatus and methods. When depositing films via electrodeposition, where the substrate has an inherent resistivity, for example, sheet resistance in a thin film, methods and apparatus of the invention are used to electrodeposit materials onto the substrate by forming a plurality of ohmic contacts to the substrate surface and thereby overcome the inherent resistance and electrodeposit uniform films. Methods and apparatus of the invention find particular use in solar cell fabrication.

    摘要翻译： 本发明一般涉及电沉积装置和方法。 当通过电沉积沉积膜时，其中衬底具有固有电阻率，例如薄膜中的薄层电阻，本发明的方法和装置用于通过在衬底表面上形成多个欧姆接触将材料电沉积到衬底上， 从而克服固有的电阻和电沉积均匀的膜。 本发明的方法和装置在太阳能电池制造中特别有用。

    Apparatus and methods for semiconductor IC failure detection
    7.
    发明授权
    Apparatus and methods for semiconductor IC failure detection 有权

    公开(公告)号：US07067335B2

    公开(公告)日：2006-06-27

    申请号：US10264625

    申请日：2002-10-02

    申请人： Kurt H. Weiner ,  Gaurav Verma

    发明人： Kurt H. Weiner ,  Gaurav Verma

    IPC分类号： G01R31/26 ,  H01L21/66

    CPC分类号： H01L22/34 ,  G01N21/9501 ,  G01R31/2644 ,  G01R31/307

    摘要： An improved voltage contrast test structure is disclosed. In general terms, the test structure can be fabricated in a single photolithography step or with a single reticle or mask. The test structure includes substructures which are designed to have a particular voltage potential pattern during a voltage contrast inspection. For example, when an electron beam is scanned across the test structure, an expected pattern of intensities are produced and imaged as a result of the expected voltage potentials of the test structure. However, when there is an unexpected pattern of voltage potentials present during the voltage contrast inspection, this indicates that a defect is present within the test structure. To produce different voltage potentials, a first set of substructures are coupled to a relatively large conductive structure, such as a large conductive pad, so that the first set of substructures charges more slowly than a second set of substructures that are not coupled to the relatively large conductive structure. Mechanisms for fabricating such a test structure are also disclosed. Additionally, searching mechanisms for quickly locating defects within such a test structure, as well as other types of voltage contrast structures, during a voltage contrast inspection are also provided.

    Apparatus and methods for determining and localization of failures in test structures using voltage contrast
    8.
    发明授权
    Apparatus and methods for determining and localization of failures in test structures using voltage contrast 有权
    用于使用电压对比度确定和定位测试结构中的故障的装置和方法

    公开(公告)号：US06861666B1

    公开(公告)日：2005-03-01

    申请号：US10282322

    申请日：2002-10-17

    申请人： Kurt H. Weiner ,  Gaurav Verma ,  Peter D. Nunan ,  Indranil De

    发明人： Kurt H. Weiner ,  Gaurav Verma ,  Peter D. Nunan ,  Indranil De

    IPC分类号： G01R31/28 ,  G01R31/307 ,  H01L23/544 ,  H01L23/58

    CPC分类号： H01L22/34 ,  G01R31/2884 ,  G01R31/307

    摘要： Disclosed is test structure that can be fabricated with minimal photolithography masking steps and in which defects may be localized to specific layers. Mechanisms for fabricating such test structures are also provided. In one embodiment, a semiconductor test structure suitable for a voltage contrast inspection is provided. The test structure includes one or more test layers corresponding to one or more product layers selected from a plurality of product layers of an integrated circuit (IC) product structure. The number of the selected one or more test layers is less than a total number of the plurality of product layers of the product structure, and the test layers include at least a first portion that is designed to have a first potential during the voltage contrast inspection and a second portion that is designed to have a second potential during the voltage contrast inspection. The first potential differs from the second potential. The selected one or more test layers which correspond to product layers are selected from the plurality of product layers such that defects found in the test layers of the test structure during the voltage contrast inspection represent a prediction of defects in the corresponding product structure.

    摘要翻译： 公开了可以用最小光刻掩模步骤制造并且其中缺陷可以定位于特定层的测试结构。 还提供了用于制造这种测试结构的机构。 在一个实施例中，提供了适用于电压对比度检查的半导体测试结构。 测试结构包括对应于从集成电路（IC）产品结构的多个产品层中选择的一个或多个产品层的一个或多个测试层。 所选择的一个或多个测试层的数量小于产品结构的多个产品层的总数，并且测试层至少包括设计成在电压对比度检查期间具有第一电位的第一部分 以及被设计为在电压对比度检查期间具有第二电位的第二部分。 第一个潜力与第二个潜力不同。 所选择的一个或多个对应于产品层的测试层选自多个产品层，使得在电压对比检查期间在测试结构的测试层中发现的缺陷代表相应产品结构中的缺陷的预测。

    ABSORBER REPAIR IN SUBSTRATE FABRICATED PHOTOVOLTAICS
    9.
    发明申请
    ABSORBER REPAIR IN SUBSTRATE FABRICATED PHOTOVOLTAICS 审中-公开
    吸收体修复基底织物光伏

    公开(公告)号：US20110312120A1

    公开(公告)日：2011-12-22

    申请号：US13151113

    申请日：2011-06-01

    申请人： Kurt H. Weiner ,  Gaurav Verma

    发明人： Kurt H. Weiner ,  Gaurav Verma

    IPC分类号： H01L31/18

    CPC分类号： H01L31/186 ,  H01L31/03923 ,  H01L31/03925 ,  Y02E10/541 ,  Y02P70/521

    摘要： The invention relates generally to methods of repairing defects in thin films. Void defects in thin films are repaired using methods that take advantage of substrate manufacturing protocols rather than conventional superstrate manufacturing protocols. Methods described herein are simple, robust and compatible with existing processes and equipment used in the manufacture of superstrate devices.

    摘要翻译： 本发明一般涉及修复薄膜缺陷的方法。 使用利用衬底制造协议而不是常规上层制造协议的方法修复薄膜中的空隙缺陷。 本文描述的方法是简单的，稳健的并且与用于制造覆盖装置的现有工艺和设备兼容。