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    Apparatus and methods for detection of systematic defects
    1.
    发明授权
    Apparatus and methods for detection of systematic defects 有权
    用于检测系统缺陷的装置和方法

    公开(公告)号：US07280945B1

    公开(公告)日：2007-10-09

    申请号：US10187567

    申请日：2002-07-01

    申请人： Kurt H. Weiner ,  Gaurav Verma ,  Indranil De

    发明人： Kurt H. Weiner ,  Gaurav Verma ,  Indranil De

    IPC分类号： G06F17/10 ,  G06F17/50

    CPC分类号： G01R31/318364

    摘要： Disclosed are mechanisms are provided for determining whether a particular integrated circuit (IC) pattern is susceptible to systematic failure, e.g., due to process fluctuations. In one embodiment, final resist patterns for such IC pattern are simulated using a sparse type simulator under various process settings. The sparse type simulator uses a model (e.g., a variable threshold resist model) for a particular photolithography process in which the IC pattern is to be fabricated. The model is generated from measurements taken from a plurality of simulated structures output from a rigorous type simulator. The simulated final resist patterns may then be analyzed to determine whether the corresponding IC pattern is susceptible to systematic failure. After an IC pattern which is susceptible to systematic failure has been found, a test structure may be fabricated from a plurality of IC patterns or cells. The cells of the test structure are arranged to have a particular pattern of voltage potential or brightness levels during a voltage contrast inspection. Mechanisms for quickly inspecting such test structures to thereby predict systematic yield of a product device containing patterns similar to the test structure cells are also disclosed.

    摘要翻译： 公开了提供用于确定特定集成电路（IC）模式是否易于系统故障（例如由于过程波动）的机制。 在一个实施例中，使用在各种处理设置下的稀疏型模拟器来模拟这种IC图案的最终抗蚀剂图案。 稀疏型模拟器对于要制造IC图案的特定光刻工艺使用模型（例如，可变阈值抗蚀剂模型）。 该模型是从从严格型模拟器输出的多个模拟结构中获得的测量产生的。 然后可以分析模拟的最终抗蚀剂图案，以确定相应的IC图案是否易于发生系统故障。 在已经发现容易发生系统故障的IC图案之后，可以从多个IC图案或单元制造测试结构。 测试结构的单元被布置成在电压对比度检查期间具有电压电位或亮度水平的特定图案。 还公开了用于快速检查这种测试结构从而预测包含类似于测试结构单元的图案的产品设备的系统产量的机制。

    Apparatus and methods for determining and localization of failures in test structures using voltage contrast
    2.
    发明授权
    Apparatus and methods for determining and localization of failures in test structures using voltage contrast 有权
    用于使用电压对比度确定和定位测试结构中的故障的装置和方法

    公开(公告)号：US06861666B1

    公开(公告)日：2005-03-01

    申请号：US10282322

    申请日：2002-10-17

    申请人： Kurt H. Weiner ,  Gaurav Verma ,  Peter D. Nunan ,  Indranil De

    发明人： Kurt H. Weiner ,  Gaurav Verma ,  Peter D. Nunan ,  Indranil De

    IPC分类号： G01R31/28 ,  G01R31/307 ,  H01L23/544 ,  H01L23/58

    CPC分类号： H01L22/34 ,  G01R31/2884 ,  G01R31/307

    摘要： Disclosed is test structure that can be fabricated with minimal photolithography masking steps and in which defects may be localized to specific layers. Mechanisms for fabricating such test structures are also provided. In one embodiment, a semiconductor test structure suitable for a voltage contrast inspection is provided. The test structure includes one or more test layers corresponding to one or more product layers selected from a plurality of product layers of an integrated circuit (IC) product structure. The number of the selected one or more test layers is less than a total number of the plurality of product layers of the product structure, and the test layers include at least a first portion that is designed to have a first potential during the voltage contrast inspection and a second portion that is designed to have a second potential during the voltage contrast inspection. The first potential differs from the second potential. The selected one or more test layers which correspond to product layers are selected from the plurality of product layers such that defects found in the test layers of the test structure during the voltage contrast inspection represent a prediction of defects in the corresponding product structure.

    摘要翻译： 公开了可以用最小光刻掩模步骤制造并且其中缺陷可以定位于特定层的测试结构。 还提供了用于制造这种测试结构的机构。 在一个实施例中，提供了适用于电压对比度检查的半导体测试结构。 测试结构包括对应于从集成电路（IC）产品结构的多个产品层中选择的一个或多个产品层的一个或多个测试层。 所选择的一个或多个测试层的数量小于产品结构的多个产品层的总数，并且测试层至少包括设计成在电压对比度检查期间具有第一电位的第一部分 以及被设计为在电压对比度检查期间具有第二电位的第二部分。 第一个潜力与第二个潜力不同。 所选择的一个或多个对应于产品层的测试层选自多个产品层，使得在电压对比检查期间在测试结构的测试层中发现的缺陷代表相应产品结构中的缺陷的预测。

    Electrical defect detection using pre-charge and sense scanning with prescribed delays
    3.
    发明授权
    Electrical defect detection using pre-charge and sense scanning with prescribed delays 有权
    电子缺陷检测使用预充电和感光扫描规定的延迟

    公开(公告)号：US07560939B1

    公开(公告)日：2009-07-14

    申请号：US11357374

    申请日：2006-02-17

    申请人： Indranil De ,  Kurt H. Weiner ,  Kenichi Kanai

    发明人： Indranil De ,  Kurt H. Weiner ,  Kenichi Kanai

    IPC分类号： G01R31/305

    CPC分类号： G01R31/307

    摘要： One embodiment relates to an electron beam apparatus. The apparatus includes a mechanism for moving a substrate relative to the electron beam column at a controlled speed. A probe beam gun is configured to generate a probe beam through the column, and a pre-charging beam gun configured to generate a pre-charging beam through the column. Control circuitry configured to pre-scan a scan line with the pre-charging beam at least once and to subsequently sense scan the scan line with the probe beam at least once. The control circuitry is further configured so that there is a prescribed delay time between said pre-scanning and said sense scanning of the scan line. In another embodiment, a single electron beam and a deflection system configured to deflect the electron beam into pre-scans and sense scans. Other embodiments and features are also disclosed.

    摘要翻译： 一个实施例涉及电子束装置。 该装置包括用于以受控的速度相对于电子束柱移动衬底的机构。 探测光束枪被配置为产生通过色谱柱的探测光束，以及配置成产生通过色谱柱的预充电束的预充电束枪。 控制电路被配置为使用预充电束预扫描扫描线至少一次，并且随后感测到用探针光束扫描扫描线至少一次。 进一步配置控制电路，使得在扫描线的所述预扫描和所述感测扫描之间存在规定的延迟时间。 在另一个实施例中，单电子束和偏转系统被配置为将电子束偏转成预扫描并感测扫描。 还公开了其它实施例和特征。