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1.发明授权公开(公告)号：US08502274B1
公开(公告)日：2013-08-06
申请号：US13441380
申请日：2012-04-06
申请人： Kurt Matoy , Thomas Detzel , Michael Nelhiebel , Arno Zechmann , Stefan Decker , Robert Illing , Sven Gustav Lanzerstorfer , Christian Djelassi , Bernhard Auer , Stefan Woehlert
发明人： Kurt Matoy , Thomas Detzel , Michael Nelhiebel , Arno Zechmann , Stefan Decker , Robert Illing , Sven Gustav Lanzerstorfer , Christian Djelassi , Bernhard Auer , Stefan Woehlert
IPC分类号： H01L23/52
CPC分类号： H01L29/7813 , H01L23/528 , H01L29/41741 , H01L29/41766 , H01L29/42368 , H01L29/7815 , H01L2924/0002 , H01L2924/00
摘要： Power transistor cells are formed in a cell array of an integrated circuit. Contact vias may electrically connect a metal structure above the cell array and the power transistor cells. A connecting line electrically connects a first element arranged in the cell array and a second element arranged in a peripheral region. A portion of the connecting line is arranged between the metal structure and the cell array and runs between a first axis and a second axis which are arranged parallel and at a distance to each other. The distance is greater than a width of the connecting line portion. The connecting line portion is tangent to both the first axis and the second axis. Shear-induced material transport along the connecting line is reduced by shortening critical portions or by exploiting grain boundary effects. The reliability of an insulator structure covering the connecting line is increased.
摘要翻译： 功率晶体管单元形成在集成电路的单元阵列中。 接触通孔可电连接单元阵列上方的金属结构和功率晶体管单元。 连接线将布置在单元阵列中的第一元件和布置在周边区域中的第二元件电连接。 连接线的一部分布置在金属结构和电池阵列之间，并且在平行且彼此间隔一定距离的第一轴和第二轴之间延伸。 距离大于连接线部分的宽度。 连接线部分与第一轴线和第二轴线相切。 通过缩短临界部分或利用晶界效应，沿着连接线的剪切诱导材料传输减少。 覆盖连接线的绝缘体结构的可靠性增加。
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公开(公告)号：US09418937B2
公开(公告)日：2016-08-16
申请号：US13315642
申请日：2011-12-09
申请人： Thomas Detzel , Johann Gross , Robert Illing , Maximilian Krug , Sven Gustav Lanzerstorfer , Michael Nelhiebel , Werner Robl , Michael Rogalli , Stefan Woehlert
发明人： Thomas Detzel , Johann Gross , Robert Illing , Maximilian Krug , Sven Gustav Lanzerstorfer , Michael Nelhiebel , Werner Robl , Michael Rogalli , Stefan Woehlert
IPC分类号： H01L23/52 , H01L23/532 , H01L21/288
CPC分类号： H01L23/3735 , H01L21/2885 , H01L21/4882 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit includes a base element and a copper element over the base element, the copper element having a thickness of at least 5 μm and a ratio of average grain size to thickness of less than 0.7.
摘要翻译： 集成电路包括在基底元件上的基底元件和铜元件，铜元素的厚度至少为5μm，平均晶粒尺寸与厚度之比小于0.7。
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公开(公告)号：US20130147047A1
公开(公告)日：2013-06-13
申请号：US13315642
申请日：2011-12-09
申请人： Thomas Detzel , Johann Gross , Robert Illing , Maximilian Krug , Sven Gustav Lanzerstorfer , Michael Nelhiebel , Werner Robl , Michael Rogalli , Stefan Woehlert
发明人： Thomas Detzel , Johann Gross , Robert Illing , Maximilian Krug , Sven Gustav Lanzerstorfer , Michael Nelhiebel , Werner Robl , Michael Rogalli , Stefan Woehlert
CPC分类号： H01L23/3735 , H01L21/2885 , H01L21/4882 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit includes a base element and a copper element over the base element, the copper element having a thickness of at least 5 μm and a ratio of average grain size to thickness of less than 0.7.
摘要翻译： 集成电路包括在基底元件上的基底元件和铜元件，铜元件具有至少5μm的厚度，并且平均晶粒尺寸与厚度之比小于0.7。
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公开(公告)号：US20080179669A1
公开(公告)日：2008-07-31
申请号：US11680320
申请日：2007-02-28
IPC分类号： H01L29/78 , H01L21/3205 , H01L23/52
CPC分类号： H01L21/76832 , H01L21/76829 , H01L21/76837 , H01L23/5329 , H01L23/53295 , H01L29/41741 , H01L29/7803 , H01L29/7813 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit including a semiconductor arrangement, a power semiconductor component and an associated production method is disclosed. One embodiment includes a carrier substrate, a first interconnect layer, formed on the carrier substrate and has at least one cutout, an insulating filling layer, formed on the first interconnect layer and the carrier substrate and fills at least one cutout, an SiON layer, formed on the filling layer, and a second interconnect layer, formed over the SiON layer.
摘要翻译： 公开了一种包括半导体装置，功率半导体元件和相关制造方法的集成电路。 一个实施例包括形成在载体基板上并具有至少一个切口的绝缘填充层的载体基板，第一互连层，形成在第一互连层和载体基板上并填充至少一个切口，SiON层， 形成在所述填充层上，以及形成在所述SiON层上的第二互连层。
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公开(公告)号：US07834427B2
公开(公告)日：2010-11-16
申请号：US11680320
申请日：2007-02-28
CPC分类号： H01L21/76832 , H01L21/76829 , H01L21/76837 , H01L23/5329 , H01L23/53295 , H01L29/41741 , H01L29/7803 , H01L29/7813 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit including a semiconductor arrangement, a power semiconductor component and an associated production method is disclosed. One embodiment includes a carrier substrate, a first interconnect layer, formed on the carrier substrate and has at least one cutout, an insulating filling layer, formed on the first interconnect layer and the carrier substrate and fills at least one cutout, an SiON layer, formed on the filling layer, and a second interconnect layer, formed over the SiON layer.
摘要翻译： 公开了一种包括半导体装置，功率半导体元件和相关制造方法的集成电路。 一个实施例包括形成在载体基板上并具有至少一个切口的绝缘填充层的载体基板，第一互连层，形成在第一互连层和载体基板上并填充至少一个切口，SiON层， 形成在所述填充层上，以及形成在所述SiON层上的第二互连层。
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6.发明申请Integrated semiconductor circuit having a logic and power metallization without intermetal dielectric 有权具有无金属间电介质的逻辑和功率金属化的集成半导体电路公开(公告)号：US20050179068A1
公开(公告)日：2005-08-18
申请号：US11037273
申请日：2005-01-18
申请人： Michael Rueb , Thomas Detzel
发明人： Michael Rueb , Thomas Detzel
IPC分类号： H01L21/336 , H01L21/768 , H01L23/522 , H01L23/528 , H01L29/417 , H01L29/45 , H01L29/78 , H01L31/113
CPC分类号： H01L23/5283 , H01L23/528 , H01L29/41741 , H01L29/41758 , H01L29/456 , H01L29/7801 , H01L29/7802 , H01L2924/0002 , H01L2924/00
摘要： An integrated semiconductor circuit having a first and a second portion of a substrate, in which a power semiconductor circuit structure and a logic circuit structure are respectively formed. The metallization having a power metal layer and an in relative terms thinner logic metal layer, the two metal layers being located directly above one another in this order, without an intermetal dielectric between them, only in the first portion above the power semiconductor circuit structure, and an uninterrupted conductive barrier layer being located at least between the power metal layer and the intermediate oxide layer and also between the power metal layer and the contact regions and electrode portions of the power semiconductor circuit structure which it contact-connects, and to a method for fabricating it.
摘要翻译： 一种具有分别形成功率半导体电路结构和逻辑电路结构的基板的第一和第二部分的集成半导体电路。 金属化具有功率金属层，并且相对于较薄的逻辑金属层，两个金属层仅在功率半导体电路结构上方的第一部分中以这种顺序依次位于彼此之间而没有金属间电介质， 以及不间断的导电阻挡层，其至少位于功率金属层和中间氧化物层之间，并且还位于功率金属层与其接触连接的功率半导体电路结构的接触区域和电极部分之间，以及方法 用于制造它。
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公开(公告)号：US08039931B2
公开(公告)日：2011-10-18
申请号：US11287736
申请日：2005-11-28
申请人： Josef Maynollo , Thomas Detzel
发明人： Josef Maynollo , Thomas Detzel
IPC分类号： H01L21/00 , H01L29/66 , H01L23/495
CPC分类号： H01L23/485 , H01L23/3157 , H01L2924/0002 , H01L2924/01046 , H01L2924/01079 , H01L2924/00
摘要： A power semiconductor component and a method for the production of a power semiconductor component are disclosed. According to one embodiment of the invention, a topmost metallization region that is provided is formed in a manner extended laterally and outside contacts formed, in such a way that, as a result, a protection and sealing material region to be provided is formed, whilst avoiding electrically insulating additional protection and sealing layers that are usually to be provided.
摘要翻译： 公开了功率半导体元件和功率半导体元件的制造方法。 根据本发明的一个实施例，提供的最上面的金属化区域以横向延伸的方式形成，并且以形成的外部触点形成，从而形成要提供的保护和密封材料区域，同时 避免电绝缘附加的保护和通常要提供的密封层。
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公开(公告)号：US20060145342A1
公开(公告)日：2006-07-06
申请号：US11287736
申请日：2005-11-28
申请人： Josef Maynollo , Thomas Detzel
发明人： Josef Maynollo , Thomas Detzel
CPC分类号： H01L23/485 , H01L23/3157 , H01L2924/0002 , H01L2924/01046 , H01L2924/01079 , H01L2924/00
摘要： A power semiconductor component and a method for the production of a power semiconductor component are disclosed. According to one embodiment of the invention, a topmost metallization region that is provided is formed in a manner extended laterally and outside contacts formed, in such a way that, as a result, a protection and sealing material region to be provided is formed, whilst avoiding electrically insulating additional protection and sealing layers that are usually to be provided.
摘要翻译： 公开了功率半导体元件和功率半导体元件的制造方法。 根据本发明的一个实施例，提供的最上面的金属化区域以横向延伸的方式形成，并且以形成的外部触点形成，从而形成要提供的保护和密封材料区域，同时 避免电绝缘附加的保护和通常要提供的密封层。
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公开(公告)号：US20110318883A1
公开(公告)日：2011-12-29
申请号：US13225675
申请日：2011-09-06
申请人： Josef Maynollo , Thomas Detzel
发明人： Josef Maynollo , Thomas Detzel
IPC分类号： H01L21/60
CPC分类号： H01L23/485 , H01L23/3157 , H01L2924/0002 , H01L2924/01046 , H01L2924/01079 , H01L2924/00
摘要： A power semiconductor component and a method for the production of a power semiconductor component are disclosed. According to one embodiment of the invention, a topmost metallization region that is provided is formed in a manner extended laterally and outside contacts formed, in such a way that, as a result, a protection and sealing material region to be provided is formed, whilst avoiding electrically insulating additional protection and sealing layers that are usually to be provided.
摘要翻译： 公开了功率半导体元件和功率半导体元件的制造方法。 根据本发明的一个实施例，提供的最上面的金属化区域以横向延伸的方式形成，并且以形成的外部触点形成，从而形成要提供的保护和密封材料区域，同时 避免电绝缘附加的保护和通常要提供的密封层。
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10.发明授权Integrated semiconductor circuit having a logic and power metallization without intermetal dielectric 有权具有无金属间电介质的逻辑和功率金属化的集成半导体电路公开(公告)号：US07132726B2
公开(公告)日：2006-11-07
申请号：US11037273
申请日：2005-01-18
申请人： Michael Rueb , Thomas Detzel
发明人： Michael Rueb , Thomas Detzel
CPC分类号： H01L23/5283 , H01L23/528 , H01L29/41741 , H01L29/41758 , H01L29/456 , H01L29/7801 , H01L29/7802 , H01L2924/0002 , H01L2924/00
摘要： An integrated semiconductor circuit having a first and a second portion of a substrate, in which a power semiconductor circuit structure and a logic circuit structure are respectively formed. The metallization having a power metal layer and an in relative terms thinner logic metal layer, the two metal layers being located directly above one another in this order, without an intermetal dielectric between them, only in the first portion above the power semiconductor circuit structure, and an uninterrupted conductive barrier layer being located at least between the power metal layer and the intermediate oxide layer and also between the power metal layer and the contact regions and electrode portions of the power semiconductor circuit structure which it contact-connects, and to a method for fabricating it.
摘要翻译： 一种具有分别形成功率半导体电路结构和逻辑电路结构的基板的第一和第二部分的集成半导体电路。 金属化具有功率金属层，并且相对于较薄的逻辑金属层，两个金属层仅在功率半导体电路结构上方的第一部分中以这种顺序依次位于彼此之间而没有金属间电介质， 以及不间断的导电阻挡层，其至少位于功率金属层和中间氧化物层之间，并且还位于功率金属层与其接触连接的功率半导体电路结构的接触区域和电极部分之间，以及方法 用于制造它。
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