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    EEPROM device having selecting transistors and method of fabricating the same
    1.
    发明授权
    EEPROM device having selecting transistors and method of fabricating the same 有权
    具有选择晶体管的EEPROM器件及其制造方法

    公开(公告)号：US07285815B2

    公开(公告)日：2007-10-23

    申请号：US11336751

    申请日：2006-01-20

    申请人： Kwang-Shik Shin ,  Han-Soo Kim ,  Sung-Hoi Hur

    发明人： Kwang-Shik Shin ,  Han-Soo Kim ,  Sung-Hoi Hur

    IPC分类号： H01L29/76

    CPC分类号： H01L27/11524 ,  H01L27/115 ,  H01L27/11521

    摘要： An EEPROM includes a device isolation layer for defining a plurality of active regions, a pair of control gates extending across the active regions and a pair of selection gates patterns that extend across the active regions and are interposed between the control gate patterns. A floating gate pattern is formed on intersection regions where the control gate patterns extend across the active regions. A lower gate pattern is formed on intersection regions where the selection gate patterns extend across the active regions. An inter-gate dielectric pattern is disposed between the control gate pattern and the floating gate pattern and a dummy dielectric pattern is disposed between the selection gate pattern and the lower gate pattern. The dummy dielectric pattern is substantially parallel to the selection gate pattern, and self-aligned with one sidewall of the selection gate pattern to overlap a predetermine width of the selection gate pattern.

    摘要翻译： EEPROM包括用于限定多个有源区的器件隔离层，跨越有源区延伸的一对控制栅极和跨越有源区延伸并插入在控制栅极图案之间的一对选择栅极图案。 浮动栅极图案形成在跨越有源区域的控制栅极图案延伸的交叉区域上。 在选择栅极图案跨越有源区域延伸的交叉区域上形成下部栅极图案。 栅极间电介质图案设置在控制栅极图案和浮置栅极图案之间，并且虚设电介质图案设置在选择栅极图案和下部栅极图案之间。 虚拟介质图案基本上平行于选择栅极图案，并且与选择栅极图案的一个侧壁自对准以重叠选择栅极图案的预定宽度。

    EEPROM device having selecting transistors and method fabricating the same
    2.
    发明申请
    EEPROM device having selecting transistors and method fabricating the same 有权
    具有选择晶体管的EEPROM器件及其制造方法

    公开(公告)号：US20060120194A1

    公开(公告)日：2006-06-08

    申请号：US11336751

    申请日：2006-01-20

    申请人： Kwang-Shik Shin ,  Han-Soo Kim ,  Sung-Hoi Hur

    发明人： Kwang-Shik Shin ,  Han-Soo Kim ,  Sung-Hoi Hur

    IPC分类号： G11C7/00

    CPC分类号： H01L27/11524 ,  H01L27/115 ,  H01L27/11521

    摘要： An EEPROM includes a device isolation layer for defining a plurality of active regions, a pair of control gates extending across the active regions and a pair of selection gates patterns that extend across the active regions and are interposed between the control gate patterns. A floating gate pattern is formed on intersection regions where the control gate patterns extend across the active regions. A lower gate pattern is formed on intersection regions where the selection gate patterns extend across the active regions. An inter-gate dielectric pattern is disposed between the control gate pattern and the floating gate pattern and a dummy dielectric pattern is disposed between the selection gate pattern and the lower gate pattern. The dummy dielectric pattern is substantially parallel to the selection gate pattern, and self-aligned with one sidewall of the selection gate pattern to overlap a predetermine width of the selection gate pattern.

    摘要翻译： EEPROM包括用于限定多个有源区的器件隔离层，跨越有源区延伸的一对控制栅极和跨越有源区延伸并插入在控制栅极图案之间的一对选择栅极图案。 浮动栅极图案形成在跨越有源区域的控制栅极图案延伸的交叉区域上。 在选择栅极图案跨越有源区域延伸的交叉区域上形成下部栅极图案。 栅极间电介质图案设置在控制栅极图案和浮置栅极图案之间，并且虚设电介质图案设置在选择栅极图案和下部栅极图案之间。 虚拟介质图案基本上平行于选择栅极图案，并且与选择栅极图案的一个侧壁自对准以重叠选择栅极图案的预定宽度。

    EEPROM device having selecting transistors and method of fabricating the same
    3.
    发明申请
    EEPROM device having selecting transistors and method of fabricating the same 有权
    具有选择晶体管的EEPROM器件及其制造方法

    公开(公告)号：US20050012140A1

    公开(公告)日：2005-01-20

    申请号：US10891803

    申请日：2004-07-14

    申请人： Kwang-Shik Shin ,  Han-Soo Kim ,  Sung-Hoi Hur

    发明人： Kwang-Shik Shin ,  Han-Soo Kim ,  Sung-Hoi Hur

    IPC分类号： H01L21/8247 ,  G11C11/34 ,  H01L27/10 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

    CPC分类号： H01L27/11524 ,  H01L27/115 ,  H01L27/11521

    摘要： An EEPROM includes a device isolation layer for defining a plurality of active regions, a pair of control gates extending across the active regions and a pair of selection gates patterns that extend across the active regions and are interposed between the control gate patterns. A floating gate pattern is formed on intersection regions where the control gate patterns extend across the active regions. A lower gate pattern is formed on intersection regions where the selection gate patterns extend across the active regions. An inter-gate dielectric pattern is disposed between the control gate pattern and the floating gate pattern and a dummy dielectric pattern is disposed between the selection gate pattern and the lower gate pattern. The dummy dielectric pattern is substantially parallel to the selection gate pattern, and self-aligned with one sidewall of the selection gate pattern to overlap a predetermine width of the selection gate pattern.

    摘要翻译： EEPROM包括用于限定多个有源区的器件隔离层，跨越有源区延伸的一对控制栅极和跨越有源区延伸并插入在控制栅极图案之间的一对选择栅极图案。 浮动栅极图案形成在跨越有源区域的控制栅极图案延伸的交叉区域上。 在选择栅极图案跨越有源区域延伸的交叉区域上形成下部栅极图案。 栅极间电介质图案设置在控制栅极图案和浮置栅极图案之间，并且虚设电介质图案设置在选择栅极图案和下部栅极图案之间。 虚拟介质图案基本上平行于选择栅极图案，并且与选择栅极图案的一个侧壁自对准以重叠选择栅极图案的预定宽度。

    EEPROM device having selecting transistors and method of fabricating the same
    4.
    发明授权
    EEPROM device having selecting transistors and method of fabricating the same 有权
    具有选择晶体管的EEPROM器件及其制造方法

    公开(公告)号：US07018894B2

    公开(公告)日：2006-03-28

    申请号：US10891803

    申请日：2004-07-14

    申请人： Kwang-Shik Shin ,  Han-Soo Kim ,  Sung-Hoi Hur

    发明人： Kwang-Shik Shin ,  Han-Soo Kim ,  Sung-Hoi Hur

    IPC分类号： H01L21/336

    CPC分类号： H01L27/11524 ,  H01L27/115 ,  H01L27/11521

    摘要： An EEPROM includes a device isolation layer for defining a plurality of active regions, a pair of control gates extending across the active regions and a pair of selection gates patterns that extend across the active regions and are interposed between the control gate patterns. A floating gate pattern is formed on intersection regions where the control gate patterns extend across the active regions. A lower gate pattern is formed on intersection regions where the selection gate patterns extend across the active regions. An inter-gate dielectric pattern is disposed between the control gate pattern and the floating gate pattern and a dummy dielectric pattern is disposed between the selection gate pattern and the lower gate pattern. The dummy dielectric pattern is substantially parallel to the selection gate pattern, and self-aligned with one sidewall of the selection gate pattern to overlap a predetermine width of the selection gate pattern.

    摘要翻译： EEPROM包括用于限定多个有源区的器件隔离层，跨越有源区延伸的一对控制栅极和跨越有源区延伸并插入在控制栅极图案之间的一对选择栅极图案。 浮动栅极图案形成在跨越有源区域的控制栅极图案延伸的交叉区域上。 在选择栅极图案跨越有源区域延伸的交叉区域上形成下部栅极图案。 栅极间电介质图案设置在控制栅极图案和浮置栅极图案之间，并且虚设电介质图案设置在选择栅极图案和下部栅极图案之间。 虚拟介质图案基本上平行于选择栅极图案，并且与选择栅极图案的一个侧壁自对准以重叠选择栅极图案的预定宽度。

    Semiconductor device with vertical structures that penetrate conductive patterns and interlayer insulating patterns
    5.
    发明授权
    Semiconductor device with vertical structures that penetrate conductive patterns and interlayer insulating patterns 有权
    具有穿透导电图案和层间绝缘图案的垂直结构的半导体器件

    公开(公告)号：US09209244B2

    公开(公告)日：2015-12-08

    申请号：US13717803

    申请日：2012-12-18

    申请人： Jae-Joo Shim ,  Han-Soo Kim ,  Woon-Kyung Lee ,  Ju-Young Lim ,  Sung-Min Hwang

    发明人： Jae-Joo Shim ,  Han-Soo Kim ,  Woon-Kyung Lee ,  Ju-Young Lim ,  Sung-Min Hwang

    IPC分类号： H01L29/06 ,  H01L27/02 ,  H01L27/115

    CPC分类号： H01L29/0657 ,  H01L27/0207 ,  H01L27/1157 ,  H01L27/11582

    摘要： Provided is a semiconductor device that includes first and second isolation patterns disposed on a substrate. Alternately stacked interlayer insulating patterns and a conductive patterns are disposed on a surface of the substrate between the first and second isolation patterns. A support pattern penetrates the conductive patterns and the interlayer insulating patterns and has a smaller width than the first and second isolation patterns. First and second vertical structures are disposed between the first isolation and the support pattern and penetrate the conductive patterns and the interlayer insulating patterns. A second vertical structure is disposed between the second isolation pattern and the support pattern and penetrates the conductive patterns and the interlayer insulating patterns. A distance between top and bottom surfaces of the support pattern is greater than a distance between a bottom surface of the support pattern and the surface of the substrate.

    摘要翻译： 提供了包括设置在基板上的第一和第二隔离图案的半导体器件。 交替层叠的层间绝缘图案和导电图案设置在第一和第二隔离图案之间的基板的表面上。 支撑图案穿透导电图案和层间绝缘图案，并且具有比第一和第二隔离图案更小的宽度。 第一和第二垂直结构设置在第一隔离和支撑图案之间并且穿透导电图案和层间绝缘图案。 第二垂直结构设置在第二隔离图案和支撑图案之间并且穿透导电图案和层间绝缘图案。 支撑图案的顶表面和底表面之间的距离大于支撑图案的底表面和基底表面之间的距离。

    Method for manufacturing an ultrahigh strength hot dip galvanized steel sheet having martensitic structure as matrix
    6.
    发明授权
    Method for manufacturing an ultrahigh strength hot dip galvanized steel sheet having martensitic structure as matrix 失效
    具有马氏体组织为基体的超高强度热浸镀锌钢板的制造方法

    公开(公告)号：US08741078B2

    公开(公告)日：2014-06-03

    申请号：US13120170

    申请日：2009-09-23

    申请人： Tae-Jin Song ,  Han-Soo Kim ,  Jai-Hyun Kwak ,  Bruno C. De Cooman

    发明人： Tae-Jin Song ,  Han-Soo Kim ,  Jai-Hyun Kwak ,  Bruno C. De Cooman

    IPC分类号： C23C2/28 ,  B32B15/01

    CPC分类号： C22C38/02 ,  C22C38/001 ,  C22C38/04 ,  C22C38/06 ,  C22C38/20 ,  C22C38/22 ,  C22C38/28 ,  C22C38/32

    摘要： The present invention relates to a hot dip galvanized steel sheet and a manufacturing method thereof. The hot dip galvanize steel sheet includes a steel sheet including a martensitic structure as a matrix, and a hot dip galvanized layer formed on the steel sheet. The steel sheet includes C of 0.05 wt % to 0.30 wt %, Mn of 0.5 wt % to 3.5 wt %, Si of 0.1 wt % to 0.8 wt %, Al of 0.01 wt % to 1.5 wt %, Cr of 0.01 wt % to 1.5 wt %, Mo of 0.01 wt % to 1.5 wt %, Ti of 0.001 wt % to 0.10 wt %, N of 5 ppm to 120 ppm, B of 3 ppm to 80 ppm, an impurity, and the remainder of Fe.

    摘要翻译： 本发明涉及一种热浸镀锌钢板及其制造方法。 热镀锌钢板包括以马氏体为基体的钢板和在钢板上形成的热浸镀锌层。 该钢板包括0.05重量％至0.30重量％的C，0.5重量％至3.5重量％的Mn，0.1重量％至0.8重量％的Si，0.01重量％至1.5重量％的Al，0.01重量％的Cr至0.01重量％ 1.5重量％，Mo为0.01重量％〜1.5重量％，Ti为0.001重量％〜0.10重量％，N为5ppm〜120ppm，B为3ppm〜80ppm，杂质，余量为Fe。

    Multiple-layer non-volatile memory devices, memory systems employing such devices, and methods of fabrication thereof
    8.
    发明授权
    Multiple-layer non-volatile memory devices, memory systems employing such devices, and methods of fabrication thereof 有权
    多层非易失性存储器件，采用这种器件的存储器系统及其制造方法

    公开(公告)号：US07936002B2

    公开(公告)日：2011-05-03

    申请号：US12456391

    申请日：2009-06-16

    申请人： Jonghyuk Kim ,  Han-Soo Kim ,  YoungSeop Rah ,  Min-sung Song ,  Jang Young Chul ,  Soon-Moon Jung ,  Wonseok Cho

    发明人： Jonghyuk Kim ,  Han-Soo Kim ,  YoungSeop Rah ,  Min-sung Song ,  Jang Young Chul ,  Soon-Moon Jung ,  Wonseok Cho

    IPC分类号： H01L29/76 ,  H01L31/036 ,  H01L31/112 ,  H01L29/94 ,  H01L31/062

    CPC分类号： H01L21/82385 ,  H01L21/8221 ,  H01L21/823425 ,  H01L21/823456 ,  H01L21/823468 ,  H01L23/481 ,  H01L23/485 ,  H01L27/0688 ,  H01L27/11526 ,  H01L27/11551 ,  H01L2224/9202 ,  H01L21/76898

    摘要： In multiple-layered memory devices, memory systems employing the same, and methods of forming such devices, a second memory device layer on a first memory device layer comprises a second substrate including a second memory cell region. The second substrate includes only a single well in the second memory cell region, the single well of the second memory cell region comprising a semiconducting material doped with impurity of one of a first type and second type. The single well defines an active region in the second memory cell region of the second substrate. Multiple second cell strings are arranged on the second substrate in the second active region. Although the second memory cell region includes only a single well, during a programming or erase operation of the memory cells of the second layer, requiring a high voltage to be applied to the single well in the substrate of the second layer, the high voltage will not interfere with the operation of the peripheral transistors of the first layer, second layer, or other layers, since they are isolated from each other. As a result, the substrate of the second layer can be prepared to have a thinner profile, and with fewer processing steps, resulting in devices with higher-density, greater reliability, and reduced fabrication costs.

    摘要翻译： 在多层存储器件中，采用该器件的存储器系统和形成这种器件的方法在第一存储器件层上的第二存储器件层包括包括第二存储单元区域的第二衬底。 第二衬底仅包括第二存储单元区域中的单个阱，第二存储单元区域的单阱包括掺杂有第一类型和第二类型之一杂质的半导体材料。 单阱限定了第二衬底的第二存储单元区域中的有源区。 多个第二电池串被布置在第二有源区域中的第二衬底上。 虽然第二存储单元区域仅包括单个阱，但是在第二层的存储单元的编程或擦除操作期间，需要向第二层的衬底中的单个阱施加高电压，高电压将 不妨碍第一层，第二层或其它层的外围晶体管的操作，因为它们彼此隔离。 结果，第二层的基底可以被制备成具有更薄的轮廓，并且具有更少的加工步骤，导致具有更高密度，更高可靠性和降低制造成本的装置。