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    Methods of forming integrated circuit electrodes and capacitors by wrinkling a layer that includes a high percentage of impurities
    3.
    发明授权
    Methods of forming integrated circuit electrodes and capacitors by wrinkling a layer that includes a high percentage of impurities 有权
    通过起皱包含高比例杂质的层来形成集成电路电极和电容器的方法

    公开(公告)号：US07700454B2

    公开(公告)日：2010-04-20

    申请号：US11462178

    申请日：2006-08-03

    申请人： Wan-don Kim ,  Jae-hyun Joo ,  Seok-jun Won ,  Jung-hee Chung ,  Jin-yong Kim ,  Suk-jin Chung

    发明人： Wan-don Kim ,  Jae-hyun Joo ,  Seok-jun Won ,  Jung-hee Chung ,  Jin-yong Kim ,  Suk-jin Chung

    IPC分类号： H01L21/20

    CPC分类号： H01L28/84 ,  H01L27/1085

    摘要： A method of fabricating a uniformly wrinkled capacitor lower electrode without the need to perform a high-temperature heat treatment and a method of fabricating a capacitor including the uniformly wrinkled capacitor lower electrode are provided. A first conductive layer is formed. Then, a second conductive layer including about 20% to about 50% of impurities is formed on the first conductive layer. Next, at least some of the impurities are exhausted from the second conductive layer by heat treating the second conductive layer. A surface of the second conductive layer is wrinkled due to the exhaustion of the impurities from the second conductive layer. A dielectric layer and an upper capacitor electrode may then be formed.

    摘要翻译： 提供一种制造均匀起皱的电容器下电极而不需要进行高温热处理的方法，以及制造包括均匀起皱的电容器下电极的电容器的方法。 形成第一导电层。 然后，在第一导电层上形成包含约20％至约50％的杂质的第二导电层。 接下来，通过热处理第二导电层，至少一些杂质从第二导电层排出。 由于来自第二导电层的杂质的耗尽，第二导电层的表面起皱。 然后可以形成电介质层和上电容器电极。

    METHODS OF FORMING INTEGRATED CIRCUIT ELECTRODES AND CAPACITORS BY WRINKLING A LAYER THAT INCLUDES A HIGH PERCENTAGE OF IMPURITIES
    4.
    发明申请
    METHODS OF FORMING INTEGRATED CIRCUIT ELECTRODES AND CAPACITORS BY WRINKLING A LAYER THAT INCLUDES A HIGH PERCENTAGE OF IMPURITIES 有权
    形成集成电路电容器和电容器的方法，包括一个包含高达百分之百的包层

    公开(公告)号：US20060263977A1

    公开(公告)日：2006-11-23

    申请号：US11462178

    申请日：2006-08-03

    申请人： Wan-don Kim ,  Jae-hyun Joo ,  Seok-jun Won ,  Jung-hee Chung ,  Jin-yong Kim ,  Suk-jin Chung

    发明人： Wan-don Kim ,  Jae-hyun Joo ,  Seok-jun Won ,  Jung-hee Chung ,  Jin-yong Kim ,  Suk-jin Chung

    IPC分类号： H01L21/8242

    CPC分类号： H01L28/84 ,  H01L27/1085

    摘要： A method of fabricating a uniformly wrinkled capacitor lower electrode without the need to perform a high-temperature heat treatment and a method of fabricating a capacitor including the uniformly wrinkled capacitor lower electrode are provided. A first conductive layer is formed. Then, a second conductive layer including about 20% to about 50% of impurities is formed on the first conductive layer. Next, at least some of the impurities are exhausted from the second conductive layer by heat treating the second conductive layer. A surface of the second conductive layer is wrinkled due to the exhaustion of the impurities from the second conductive layer. A dielectric layer and an upper capacitor electrode may then be formed.

    摘要翻译： 提供一种制造均匀起皱的电容器下电极而不需要执行高温热处理的方法，以及制造包括均匀起皱的电容器下电极的电容器的方法。 形成第一导电层。 然后，在第一导电层上形成包含约20％至约50％的杂质的第二导电层。 接下来，通过热处理第二导电层，至少一些杂质从第二导电层排出。 由于来自第二导电层的杂质的耗尽，第二导电层的表面起皱。 然后可以形成电介质层和上电容器电极。

    Methods of fabricating metal-insulator-metal capacitors with a chemical barrier layer in a lower electrode
    6.
    发明授权
    Methods of fabricating metal-insulator-metal capacitors with a chemical barrier layer in a lower electrode 有权
    在下电极中制造具有化学阻挡层的金属 - 绝缘体 - 金属电容器的方法

    公开(公告)号：US07655519B2

    公开(公告)日：2010-02-02

    申请号：US11216639

    申请日：2005-09-01

    申请人： Eun-ae Chung ,  Jae-hyoung Choi ,  Jung-hee Chung ,  Young-sun Kim ,  Cha-young Yoo

    发明人： Eun-ae Chung ,  Jae-hyoung Choi ,  Jung-hee Chung ,  Young-sun Kim ,  Cha-young Yoo

    IPC分类号： H01L21/8242

    CPC分类号： H01L21/7687 ,  H01L27/10852 ,  H01L28/65 ,  H01L28/75

    摘要： A metal-insulator-metal (MIM) capacitor includes a lower electrode, a dielectric layer, and an upper electrode. The lower electrode includes a first conductive layer, a chemical barrier layer on the first conductive layer, and a second conductive layer on the chemical barrier layer. The chemical barrier layer is between the first and second conductive layers and is a different material than the first and second conductive layers. The dielectric layer is on the lower electrode. The upper electrode is on the dielectric layer opposite to the lower electrode. The first and second conductive layers can have the same thickness. The chemical barrier layer can be thinner than each of the first and second conductive layers. Related methods are discussed.

    摘要翻译： 金属绝缘体金属（MIM）电容器包括下电极，电介质层和上电极。 下电极包括第一导电层，第一导电层上的化学阻挡层和化学阻挡层上的第二导电层。 化学屏障层位于第一和第二导电层之间，并且是与第一和第二导电层不同的材料。 介电层位于下电极上。 上电极位于与下电极相对的电介质层上。 第一和第二导电层可以具有相同的厚度。 化学阻挡层可以比第一和第二导电层中的每一个薄。 讨论相关方法。

    Method of manufacturing capacitor by performing multi-stepped wet treatment on surface of electrode
    7.
    发明授权
    Method of manufacturing capacitor by performing multi-stepped wet treatment on surface of electrode 有权
    通过对电极表面进行多级湿处理来制造电容器的方法

    公开(公告)号：US07008837B2

    公开(公告)日：2006-03-07

    申请号：US10776053

    申请日：2004-02-11

    申请人： Seok-jun Won ,  Jung-hee Chung ,  Yong-kuk Jeong ,  Se-hoon Oh ,  Dae-jin Kwon ,  Cha-young Yoo

    发明人： Seok-jun Won ,  Jung-hee Chung ,  Yong-kuk Jeong ,  Se-hoon Oh ,  Dae-jin Kwon ,  Cha-young Yoo

    IPC分类号： H01L21/8242

    CPC分类号： H01L21/02068 ,  H01L27/10852 ,  H01L28/65 ,  H01L28/91

    摘要： In a method of manufacturing a capacitor by performing a multi-stepped wet treatment on the surface of a metal electrode, a lower metal electrode of a capacitor is formed, and a primary wet treatment is performed on the surface of the lower metal electrode to remove unwanted surface oxides that may exist on the surface of the lower metal electrode. A secondary wet treatment is then performed on the surface of the lower metal electrode by using a different etchant than the etchant used in the primary wet treatment, in order to remove unwanted surface organic materials that may exist on the surface of the lower metal electrode. A dielectric layer is then formed on the lower metal electrode using a high-k dielectric material. An upper metal electrode is formed on the dielectric layer.

    摘要翻译： 在通过对金属电极的表面进行多级湿式处理来制造电容器的方法中，形成电容器的下部金属电极，并对下部金属电极的表面进行一次湿式处理以除去 可能存在于下金属电极表面的不希望的表面氧化物。 然后通过使用与初次湿处理中使用的蚀刻剂不同的蚀刻剂在下金属电极的表面上进行二次湿处理，以便去除可能存在于下金属电极表面上的不希望的表面有机材料。 然后使用高k电介质材料在下金属电极上形成电介质层。 在电介质层上形成上金属电极。

    METHODS OF FORMING INTEGRATED CIRCUIT CAPACITORS HAVING COMPOSITE DIELECTRIC LAYERS THEREIN CONTAINING CRYSTALLIZATION INHIBITING REGIONS
    9.
    发明申请
    METHODS OF FORMING INTEGRATED CIRCUIT CAPACITORS HAVING COMPOSITE DIELECTRIC LAYERS THEREIN CONTAINING CRYSTALLIZATION INHIBITING REGIONS 审中-公开
    形成具有包含结晶区域的复合介电层的集成电路电容器的方法

    公开(公告)号：US20130130465A1

    公开(公告)日：2013-05-23

    申请号：US13716901

    申请日：2012-12-17

    申请人： Jae-hyoung Choi ,  Jung-hee Chung ,  Cha-young Yoo ,  Young-sun Kim ,  Se-hoo Oh

    发明人： Jae-hyoung Choi ,  Jung-hee Chung ,  Cha-young Yoo ,  Young-sun Kim ,  Se-hoo Oh

    IPC分类号： H01L29/92

    CPC分类号： H01L29/92 ,  H01L27/10852 ,  H01L28/40

    摘要： Integrated circuit capacitors have composite dielectric layers therein. These composite dielectric layers include crystallization inhibiting regions that operate to increase the overall crystallization temperature of the composite dielectric layer. An integrated circuit capacitor includes first and second capacitor electrodes and a capacitor dielectric layer extending between the first and second capacitor electrodes. The capacitor dielectric layer includes a composite of a first dielectric layer extending adjacent the first capacitor electrode, a second dielectric layer extending adjacent the second capacitor electrode and an electrically insulating crystallization inhibiting layer extending between the first and second dielectric layers. The electrically insulating crystallization inhibiting layer is formed of a material having a higher crystallization temperature characteristic relative to the first and second dielectric layers.

    摘要翻译： 集成电路电容器在其中具有复合电介质层。 这些复合电介质层包括用于增加复合介电层的整体结晶温度的结晶抑制区。 集成电路电容器包括第一和第二电容器电极和在第一和第二电容器电极之间延伸的电容器介电层。 电容器介电层包括邻近第一电容器电极延伸的第一电介质层，邻近第二电容器电极延伸的第二电介质层和在第一和第二电介质层之间延伸的电绝缘的结晶抑制层的复合材料。 电绝缘结晶抑制层由相对于第一和第二介电层具有较高结晶温度特性的材料形成。