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    MEMORY SYSTEM WITH INTERLEAVED ADDRESSING METHOD
    1.
    发明申请
    MEMORY SYSTEM WITH INTERLEAVED ADDRESSING METHOD 审中-公开
    具有异步寻址方法的记忆系统

    公开(公告)号：US20120246395A1

    公开(公告)日：2012-09-27

    申请号：US13426259

    申请日：2012-03-21

    申请人： Kyoung Lae Cho ,  Hong Rak Son ,  Eun Chu Oh

    发明人： Kyoung Lae Cho ,  Hong Rak Son ,  Eun Chu Oh

    IPC分类号： G06F12/00

    CPC分类号： G06F12/0246 ,  G06F11/073 ,  G06F11/076 ,  G06F11/0793 ,  G06F12/0638

    摘要： Disclosed is a memory system which includes a nonvolatile memory device including a memory cell array having a plurality of word lines including a first set of word lines storing first data having a high bit error rate, and a second set of word lines storing second data having low bit error rate less than the high bit error rate, and a memory controller that during a program operation maps logical addresses for a portion of the first data and a portion of the second data onto a selected word line selected from the plurality of word lines.

    摘要翻译： 公开了一种包括非易失性存储器件的存储器系统，该非易失性存储器件包括具有多个字线的存储单元阵列，该多个字线包括存储具有高误码率的第一数据的第一组字线和存储具有第二数据的第二数据的第二组， 低位错误率低于高位误码率;以及存储器控制器，其在编程操作期间将用于所述第一数据的一部分和所述第二数据的一部分的逻辑地址映射到从所述多个字线中选择的所选字线上 。

    Memory device and method of programming thereof
    5.
    发明授权
    Memory device and method of programming thereof 有权
    存储器件及其编程方法

    公开(公告)号：US08004891B2

    公开(公告)日：2011-08-23

    申请号：US12453964

    申请日：2009-05-28

    申请人： Yong June Kim ,  Kyoung Lae Cho ,  Jae Hong Kim ,  Jun Jin Kong ,  Hong Rak Son

    发明人： Yong June Kim ,  Kyoung Lae Cho ,  Jae Hong Kim ,  Jun Jin Kong ,  Hong Rak Son

    IPC分类号： G11C16/04

    CPC分类号： G11C11/5628 ,  G11C7/1006

    摘要： Example embodiments may provide a memory device and memory data programming method. The memory device according to example embodiments may encode a first data page to generate at least one first codeword and encode a second data page to generate a second codeword. The memory device may generate the first codeword with at least one of a maximum value of a number of successive ones and a second maximum value of a number of successive zeros. The memory device may program the at least one first codeword and the at least one second codeword to a plurality of multi-bit cells.

    摘要翻译： 示例性实施例可以提供存储器设备和存储器数据编程方法。 根据示例性实施例的存储器件可编码第一数据页以产生至少一个第一码字，并对第二数据页进行编码以产生第二码字。 存储器装置可以利用连续零个数的最大值和连续零数的第二最大值中的至少一个来生成第一码字。 存储器件可以将至少一个第一代码字和至少一个第二代码字编程到多个多位单元。

    DATA STORAGE DEVICE AND PROGRAM METHOD THEREOF
    7.
    发明申请
    DATA STORAGE DEVICE AND PROGRAM METHOD THEREOF 有权
    数据存储设备及其程序方法

    公开(公告)号：US20110276857A1

    公开(公告)日：2011-11-10

    申请号：US13103460

    申请日：2011-05-09

    申请人： Yong June Kim ,  Kyoung Lae Cho ,  Hong Rak Son

    发明人： Yong June Kim ,  Kyoung Lae Cho ,  Hong Rak Son

    IPC分类号： G06F12/00 ,  G06F11/10 ,  H03M13/05

    CPC分类号： G06F11/1048 ,  G11C29/10 ,  G11C2029/0411 ,  H03M7/46

    摘要： A data storage device includes a non-volatile memory device including a plurality of memory cells and a memory controller. The memory controller is configured to modify an arrangement of program data and to program the modified program data into the plurality of memory cells. The memory controller modifies the program data to eliminate a given data pattern causing physical interference between adjacent memory cells from the modified program data.

    摘要翻译： 数据存储装置包括包括多个存储器单元和存储器控制器的非易失性存储器件。 存储器控制器被配置为修改程序数据的布置并且将修改的程序数据编程到多个存储器单元中。 存储器控制器修改程序数据以消除给定的数据模式，从修改的程序数据导致相邻存储器单元之间的物理干扰。

    Memory device and method of programming thereof
    8.
    发明申请
    Memory device and method of programming thereof 有权
    存储器件及其编程方法

    公开(公告)号：US20100020620A1

    公开(公告)日：2010-01-28

    申请号：US12453964

    申请日：2009-05-28

    申请人： Yong June Kim ,  Kyoung Lae Cho ,  Jae Hong Kim ,  Jun Jin Kong ,  Hong Rak Son

    发明人： Yong June Kim ,  Kyoung Lae Cho ,  Jae Hong Kim ,  Jun Jin Kong ,  Hong Rak Son

    IPC分类号： G11C16/04 ,  G06F12/00

    CPC分类号： G11C11/5628 ,  G11C7/1006

    摘要： Example embodiments may provide a memory device and memory data programming method. The memory device according to example embodiments may encode a first data page to generate at least one first codeword and encode a second data page to generate a second codeword. The memory device may generate the first codeword with at least one of a maximum value of a number of successive ones and a second maximum value of a number of successive zeros. The memory device may program the at least one first codeword and the at least one second codeword to a plurality of multi-bit cells.

    摘要翻译： 示例性实施例可以提供存储器设备和存储器数据编程方法。 根据示例性实施例的存储器件可编码第一数据页以产生至少一个第一码字，并对第二数据页进行编码以产生第二码字。 存储器装置可以利用连续零个数的最大值和连续零数的第二最大值中的至少一个来生成第一码字。 存储器件可以将至少一个第一代码字和至少一个第二代码字编程到多个多位单元。

    NONVOLATILE MEMORY DEVICES AND METHODS OF OPERATING NONVOLATILE MEMORY DEVICES
    9.
    发明申请
    NONVOLATILE MEMORY DEVICES AND METHODS OF OPERATING NONVOLATILE MEMORY DEVICES 有权
    非易失性存储器件和操作非易失性存储器件的方法

    公开(公告)号：US20120257455A1

    公开(公告)日：2012-10-11

    申请号：US13211743

    申请日：2011-08-17

    申请人： Eun Chu Oh ,  Hong Rak Son ,  KyoungLae Cho ,  Junjin Kong

    发明人： Eun Chu Oh ,  Hong Rak Son ,  KyoungLae Cho ,  Junjin Kong

    IPC分类号： G11C16/10

    CPC分类号： G11C16/10 ,  G11C16/0483 ,  G11C16/3454

    摘要： Methods of operating nonvolatile memory devices including a plurality of cell strings each having at least one ground selection transistor, a plurality of memory cells, and at least one string selection transistor, the operating methods including receiving a command and an address, determining a voltage applying time in response to the input command and address, and applying a specific voltage to memory cells of cell strings corresponding to the input address during the determined voltage applying time.

    摘要翻译： 操作包括多个单元串的非易失性存储器件的方法，每个单元串具有至少一个接地选择晶体管，多个存储单元和至少一个串选择晶体管，所述操作方法包括接收命令和地址，确定施加的电压 响应于输入命令和地址的时间，以及在确定的电压施加时间期间，将特定电压施加到对应于输入地址的单元串的存储单元。

    Nonvolatile memory storage system
    10.
    发明授权
    Nonvolatile memory storage system 有权

    公开(公告)号：US10229749B2

    公开(公告)日：2019-03-12

    申请号：US15475670

    申请日：2017-03-31

    申请人： Eun Chu Oh ,  Pilsang Yoon ,  Jun Jin Kong ,  Hong Rak Son ,  Dongsup Jin

    发明人： Eun Chu Oh ,  Pilsang Yoon ,  Jun Jin Kong ,  Hong Rak Son ,  Dongsup Jin

    IPC分类号： G11C29/50 ,  G11C16/04 ,  G11C16/26 ,  G11C16/10

    摘要： A nonvolatile memory storage system includes a plurality of memory cells and a memory controller configured to transmit a read command to a nonvolatile memory device based on a plurality of read voltages. The nonvolatile memory device performs a first read operation on a first level among the N levels based on a first read voltage among the plurality of read voltages, counts the number of on-cells that respond to the first read voltage among the plurality of memory cells, and adjusts a level of a second read voltage to be used to perform a second read operation on the first level or a second level among the N levels among the plurality of read voltages according to a comparison result of the counted number of on-cells and the number of reference cells.