公开(公告)号：US08706953B2

公开(公告)日：2014-04-22

申请号：US13096036

申请日：2011-04-28

申请人： Kyoung Lae Cho ,  Kwang Ho Kim ,  Jun Jin Kong ,  Jaehong Kim ,  Hong Rak Son

发明人： Kyoung Lae Cho ,  Kwang Ho Kim ,  Jun Jin Kong ,  Jaehong Kim ,  Hong Rak Son

IPC分类号： G06F12/02

CPC分类号： H03M7/30

摘要： A method of storing data in a storage medium of a data storage device comprises storing input data in the storage medium, and reading the input data from the storage medium and compressing the read data during a background operation of the data storage device.

摘要翻译： 一种在数据存储装置的存储介质中存储数据的方法包括将输入数据存储在存储介质中，并从存储介质读取输入数据，并在数据存储装置的后台操作期间压缩读取的数据。

公开(公告)号：US08004891B2

公开(公告)日：2011-08-23

申请号：US12453964

申请日：2009-05-28

申请人： Yong June Kim ,  Kyoung Lae Cho ,  Jae Hong Kim ,  Jun Jin Kong ,  Hong Rak Son

发明人： Yong June Kim ,  Kyoung Lae Cho ,  Jae Hong Kim ,  Jun Jin Kong ,  Hong Rak Son

IPC分类号： G11C16/04

CPC分类号： G11C11/5628 ,  G11C7/1006

摘要： Example embodiments may provide a memory device and memory data programming method. The memory device according to example embodiments may encode a first data page to generate at least one first codeword and encode a second data page to generate a second codeword. The memory device may generate the first codeword with at least one of a maximum value of a number of successive ones and a second maximum value of a number of successive zeros. The memory device may program the at least one first codeword and the at least one second codeword to a plurality of multi-bit cells.

摘要翻译： 示例性实施例可以提供存储器设备和存储器数据编程方法。 根据示例性实施例的存储器件可编码第一数据页以产生至少一个第一码字，并对第二数据页进行编码以产生第二码字。 存储器装置可以利用连续零个数的最大值和连续零数的第二最大值中的至少一个来生成第一码字。 存储器件可以将至少一个第一代码字和至少一个第二代码字编程到多个多位单元。

公开(公告)号：US09009390B2

公开(公告)日：2015-04-14

申请号：US13238749

申请日：2011-09-21

申请人： Seong Hyeog Choi ,  Hong Rak Son ,  Kyoung Lae Cho ,  Jun Jin Kong ,  Sang Hoon Lee

发明人： Seong Hyeog Choi ,  Hong Rak Son ,  Kyoung Lae Cho ,  Jun Jin Kong ,  Sang Hoon Lee

IPC分类号： G06F13/00 ,  G06F13/28 ,  G11C16/02 ,  G11C16/06 ,  G11C29/42 ,  G11C16/00 ,  G11C11/56 ,  G11C16/34

CPC分类号： G11C16/02 ,  G06F13/00 ,  G11C11/5642 ,  G11C16/00 ,  G11C16/06 ,  G11C16/3418 ,  G11C16/349 ,  G11C29/42

摘要： A memory system including a non-volatile memory device and a memory controller is provided. When a read operation on a first data initially output from the non-volatile memory device during a first read operation is successful, the memory controller may change a read voltage for reading a second data stored in the non-volatile memory device during a second read operation.

摘要翻译： 提供了包括非易失性存储器件和存储器控制器的存储器系统。 当在第一次读取操作期间最初从非易失性存储器件输出的第一数据的读取操作成功时，存储器控制器可以在第二次读取期间改变用于读取存储在非易失性存储器件中的第二数据的读取电压 操作。

公开(公告)号：US20100020620A1

公开(公告)日：2010-01-28

申请号：US12453964

申请日：2009-05-28

申请人： Yong June Kim ,  Kyoung Lae Cho ,  Jae Hong Kim ,  Jun Jin Kong ,  Hong Rak Son

发明人： Yong June Kim ,  Kyoung Lae Cho ,  Jae Hong Kim ,  Jun Jin Kong ,  Hong Rak Son

IPC分类号： G11C16/04 ,  G06F12/00

CPC分类号： G11C11/5628 ,  G11C7/1006

摘要： Example embodiments may provide a memory device and memory data programming method. The memory device according to example embodiments may encode a first data page to generate at least one first codeword and encode a second data page to generate a second codeword. The memory device may generate the first codeword with at least one of a maximum value of a number of successive ones and a second maximum value of a number of successive zeros. The memory device may program the at least one first codeword and the at least one second codeword to a plurality of multi-bit cells.

摘要翻译： 示例性实施例可以提供存储器设备和存储器数据编程方法。 根据示例性实施例的存储器件可编码第一数据页以产生至少一个第一码字，并对第二数据页进行编码以产生第二码字。 存储器装置可以利用连续零个数的最大值和连续零数的第二最大值中的至少一个来生成第一码字。 存储器件可以将至少一个第一代码字和至少一个第二代码字编程到多个多位单元。

公开(公告)号：US20120131266A1

公开(公告)日：2012-05-24

申请号：US13301961

申请日：2011-11-22

申请人： Kyoung Lae CHO ,  Kwang Ho Kim ,  Jun Jin Kong ,  Jin Kyu Kim

发明人： Kyoung Lae CHO ,  Kwang Ho Kim ,  Jun Jin Kong ,  Jin Kyu Kim

IPC分类号： G06F12/00

CPC分类号： G06F12/04 ,  G06F2212/401

摘要： A data storage system includes a controller configured to receive data and data information about the data from a host, analyze the data information, detect whether the data has been compressed, and compress the data according to a detection result; and a nonvolatile memory device configured to store the data compressed by the controller and information about whether the data has been compressed. The controller includes a buffer configured to temporarily store the data and the data information received from the host, an analyzer configured to output, based on an analysis result, a compression control flag that indicates whether the data has been compressed, and a compressor configured to selectively compress or bypass the data based on the compression control flag, and to transmit the data to the nonvolatile memory device.

摘要翻译： 数据存储系统包括控制器，被配置为从主机接收关于数据的数据和数据信息，分析数据信息，检测数据是否已被压缩，并根据检测结果压缩数据; 以及非易失性存储装置，被配置为存储由所述控制器压缩的数据以及关于所述数据是否被压缩的信息。 所述控制器包括被配置为临时存储从所述主机接收到的数据和数据信息的缓冲器，分析器，被配置为基于分析结果输出指示所述数据是否已被压缩的压缩控制标志，以及压缩器， 基于压缩控制标志选择性地压缩或旁路数据，并将数据发送到非易失性存储器件。

公开(公告)号：US20090182934A1

公开(公告)日：2009-07-16

申请号：US12155647

申请日：2008-06-06

申请人： Jaehong Kim ,  Kyoung Lae Cho ,  Jun Jin Kong ,  Heeseok Eun ,  Seung-Hwan Song

发明人： Jaehong Kim ,  Kyoung Lae Cho ,  Jun Jin Kong ,  Heeseok Eun ,  Seung-Hwan Song

IPC分类号： G06F12/02 ,  G11C16/04 ,  G11C7/00

CPC分类号： G11C11/5628 ,  G11C11/5671 ,  G11C29/00

摘要： Memory devices and multi-bit programming methods are provided. A memory device may include a plurality of memory units; a data separator that separates data into a plurality of groups; a selector that rotates each of the plurality of groups and transmits each of the groups to at least one of the plurality of memory units. The plurality of memory units may include page buffers that may program the transmitted group in a plurality of multi-bit cell arrays using a different order of a page programming operation. Through this, evenly reliable data pages may be generated.

摘要翻译： 提供了存储器件和多位编程方法。 存储器件可以包括多个存储器单元; 数据分离器，将数据分离成多个组; 选择器，其使所述多个组中的每一个旋转，并将所述组中的每一个发送到所述多个存储器单元中的至少一个。 多个存储器单元可以包括可以使用页面编程操作的不同顺序对多个多位单元阵列中的发送组进行编程的页缓冲器。 通过此，可能会生成均匀可靠的数据页。

公开(公告)号：US08230157B2

公开(公告)日：2012-07-24

申请号：US12155647

申请日：2008-06-06

申请人： Jaehong Kim ,  Kyoung Lae Cho ,  Jun Jin Kong ,  Heeseok Eun ,  Seung-Hwan Song

发明人： Jaehong Kim ,  Kyoung Lae Cho ,  Jun Jin Kong ,  Heeseok Eun ,  Seung-Hwan Song

IPC分类号： G06F12/00 ,  G06F13/00 ,  G06F13/28 ,  G06F11/00 ,  G06F11/10 ,  H03M13/00 ,  G11C29/00

CPC分类号： G11C11/5628 ,  G11C11/5671 ,  G11C29/00

摘要： Memory devices and multi-bit programming methods are provided. A memory device may include a plurality of memory units; a data separator that separates data into a plurality of groups; a selector that rotates each of the plurality of groups and transmits each of the groups to at least one of the plurality of memory units. The plurality of memory units may include page buffers that may program the transmitted group in a plurality of multi-bit cell arrays using a different order of a page programming operation. Through this, evenly reliable data pages may be generated.

摘要翻译： 提供了存储器件和多位编程方法。 存储器件可以包括多个存储器单元; 数据分离器，将数据分离成多个组; 选择器，其使所述多个组中的每一个旋转，并将所述组中的每一个发送到所述多个存储器单元中的至少一个。 多个存储器单元可以包括可以使用页面编程操作的不同顺序对多个多位单元阵列中的发送组进行编程的页缓冲器。 通过此，可能会生成均匀可靠的数据页。

公开(公告)号：US08773922B2

公开(公告)日：2014-07-08

申请号：US12614545

申请日：2009-11-09

申请人： Seung-Hwan Song ,  Jaehong Kim ,  Kyoung Lae Cho ,  Yong June Kim ,  Jun Jin Kong ,  Jong Han Kim

发明人： Seung-Hwan Song ,  Jaehong Kim ,  Kyoung Lae Cho ,  Yong June Kim ,  Jun Jin Kong ,  Jong Han Kim

IPC分类号： G11C7/06

CPC分类号： G11C16/26 ,  G11C11/5642 ,  G11C29/00 ,  G11C2211/5634

摘要： A non-volatile semiconductor memory device and related method of determining a read voltage are disclosed. The non-volatile semiconductor memory device includes; a memory cell array including a plurality of memory cells, a read voltage determination unit configured to determine an optimal read voltage by comparing reference data obtained during a program operation with comparative data obtained during a subsequent read operation and changing a current read voltage to a new read voltage based on a result of the comparison, and a read voltage generation unit configured to generate the new read voltage in response to a read voltage control signal provided by the read voltage determination unit.

摘要翻译： 公开了一种非易失性半导体存储器件及确定读取电压的相关方法。 非易失性半导体存储器件包括： 包括多个存储单元的存储单元阵列，读电压确定单元，被配置为通过将在编程操作期间获得的参考数据与在随后的读取操作期间获得的比较数据进行比较来确定最佳读取电压，并将当前读取电压改变为新的 基于比较结果的读取电压和读取电压生成单元，被配置为响应于由读取电压确定单元提供的读取电压控制信号而产生新的读取电压。

公开(公告)号：US08441862B2

公开(公告)日：2013-05-14

申请号：US13080809

申请日：2011-04-06

申请人： Hong Rak Son ,  Han Woong Yoo ,  Jaehong Kim ,  Jun Jin Kong

发明人： Hong Rak Son ,  Han Woong Yoo ,  Jaehong Kim ,  Jun Jin Kong

IPC分类号： G11C16/06

CPC分类号： G11C11/5628 ,  G11C16/3436

摘要： Provided is a program method of a multi-bit memory device with memory cells arranged in rows and columns. The program method includes a programming each memory cell of the first group of memory cells to a state within a first group of states according to a verify voltage level of a first group of verify voltage levels within a first range of levels, and programming each memory cell of the second group of memory cells to a state within a second group of states according to a verify voltage level of a second group of verify voltage levels within a second range of levels. The lowest verify voltage level in the second range of levels is higher than the highest verify voltage level in the first range of levels. A first voltage difference between adjacent verify voltage levels within the first range of levels is different from a second voltage difference between the highest verify voltage level of the second group of verify voltage levels and the lowest verify voltage level of the third group of verify voltage levels.

摘要翻译： 提供了具有排列成行和列的存储单元的多位存储器件的编程方法。 程序方法包括根据第一级别的第一组验证电压电平的验证电压电平将第一组存储器单元的每个存储器单元编程到第一组状态内的状态，以及编程每个存储器 第二组存储器单元的单元根据在第二级别范围内的第二组验证电压电平的验证电压电平而处于第二组状态内的状态。 第二级别的最低验证电压电平高于第一级别范围内的最高验证电压电平。 在第一级别范围内的相邻验证电压电平之间的第一电压差不同于第二组验证电压电平的最高验证电压电平与第三组验证电压电平的最低验证电压电平之间的第二电压差 。

公开(公告)号：US20110249496A1

公开(公告)日：2011-10-13

申请号：US13080809

申请日：2011-04-06

申请人： Hong Rak Son ,  Han Woong Yoo ,  Jaehong Kim ,  Jun Jin Kong

发明人： Hong Rak Son ,  Han Woong Yoo ,  Jaehong Kim ,  Jun Jin Kong

IPC分类号： G11C16/10

CPC分类号： G11C11/5628 ,  G11C16/3436

摘要： Provided is a program method of a multi-bit memory device with memory cells arranged in rows and columns. The program method includes a programming each memory cell of the first group of memory cells to a state within a first group of states according to a verify voltage level of a first group of verify voltage levels within a first range of levels, and programming each memory cell of the second group of memory cells to a state within a second group of states according to a verify voltage level of a second group of verify voltage levels within a second range of levels. The lowest verify voltage level in the second range of levels is higher than the highest verify voltage level in the first range of levels. A first voltage difference between adjacent verify voltage levels within the first range of levels is different from a second voltage difference between the highest verify voltage level of the second group of verify voltage levels and the lowest verify voltage level of the third group of verify voltage levels.

摘要翻译： 提供了具有排列成行和列的存储单元的多位存储器件的编程方法。 程序方法包括根据第一级别的第一组验证电压电平的验证电压电平将第一组存储器单元的每个存储器单元编程到第一组状态内的状态，以及编程每个存储器 第二组存储器单元的单元根据在第二级别范围内的第二组验证电压电平的验证电压电平而处于第二组状态内的状态。 第二级别的最低验证电压电平高于第一级别范围内的最高验证电压电平。 在第一级别范围内的相邻验证电压电平之间的第一电压差不同于第二组验证电压电平的最高验证电压电平与第三组验证电压电平的最低验证电压电平之间的第二电压差 。