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    Methods of forming integrated circuit devices having metal interconnect structures therein
    8.
    发明授权
    Methods of forming integrated circuit devices having metal interconnect structures therein 失效
    形成其中具有金属互连结构的集成电路器件的方法

    公开(公告)号：US07435673B2

    公开(公告)日：2008-10-14

    申请号：US11237987

    申请日：2005-09-28

    申请人： Kyoung Woo Lee ,  Ja-Hum Ku ,  Duk Ho Hong ,  Wan Jae Park

    发明人： Kyoung Woo Lee ,  Ja-Hum Ku ,  Duk Ho Hong ,  Wan Jae Park

    IPC分类号： H01L21/4763

    CPC分类号： H01L21/7684 ,  H01L21/76801 ,  H01L21/76802 ,  H01L21/76877

    摘要： Methods of forming metal interconnect structures include forming a first electrically insulating layer on a semiconductor substrate and forming a second electrically insulating layer on the first electrically insulating layer. The second and first electrically insulating layers are selectively etched in sequence to define a contact hole therein. A first metal layer (e.g., tungsten) is deposited. This first metal layer extends on the second electrically insulating layer and into the contact hole. The first metal layer is then patterned to expose the second electrically insulating layer. The second electrically insulating layer is selectively etched for a sufficient duration to expose the first electrically insulating layer and expose a metal plug within the contact hole. This selective etching step is performed using the patterned first metal layer as an etching mask. A seam within the exposed metal plug is then filled with an electrically conductive filler material (e.g., CoWP). A second metal layer is then formed on the exposed metal plug containing the electrically conductive filler material.

    摘要翻译： 形成金属互连结构的方法包括在半导体衬底上形成第一电绝缘层，并在第一电绝缘层上形成第二电绝缘层。 依次选择性地蚀刻第二和第一电绝缘层以在其中限定接触孔。 沉积第一金属层（例如钨）。 该第一金属层在第二电绝缘层上延伸并进入接触孔。 然后将第一金属层图案化以暴露第二电绝缘层。 选择性地蚀刻第二电绝缘层足够的持续时间以暴露第一电绝缘层并在接触孔内露出金属插塞。 使用图案化的第一金属层作为蚀刻掩模来执行该选择性蚀刻步骤。 暴露的金属插头内的接缝然后用导电填充材料（例如，CoWP）填充。 然后在暴露的包含导电填料的金属塞上形成第二金属层。

    Methods of forming integrated circuit devices having metal interconnect layers therein
    10.
    发明授权
    Methods of forming integrated circuit devices having metal interconnect layers therein 有权

    公开(公告)号：US07282451B2

    公开(公告)日：2007-10-16

    申请号：US11216686

    申请日：2005-08-31

    申请人： Duk Ho Hong ,  Kyoung Woo Lee ,  Markus Naujok ,  Roman Knoefler

    发明人： Duk Ho Hong ,  Kyoung Woo Lee ,  Markus Naujok ,  Roman Knoefler

    IPC分类号： H01L21/302

    CPC分类号： C25D5/022 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/485 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Methods of forming metal interconnect layers include forming an electrically insulating layer having a contact hole therein, on a semiconductor substrate and then forming a recess in the electrically insulating layer, at a location adjacent the contact hole. The contact hole and the recess are then filled with a first electrically conductive material (e.g., tungsten (W)). At least a portion of the first electrically conductive material within the contact hole is then exposed. This exposure occurs by etching back a portion of the electrically insulating layer using the first electrically conductive material within the contact hole and within the recess as an etching mask. The first electrically conductive material within the recess is then removed to expose another portion of the electrically insulating layer. Following this, the exposed portion of the first electrically conductive material is covered with a second electrically conductive material (e.g., copper (Cu)), which directly contacts the exposed portion of the first electrically conductive material. This covering step results in the definition of a wiring pattern including the first and second electrically conductive materials.