公开(公告)号：US20120153500A1

公开(公告)日：2012-06-21

申请号：US13314575

申请日：2011-12-08

申请人： Kyoung-Hee KIM ,  Gil-Heyun CHOI ,  Kyu-Hee HAN ,  Byung-Lyul PARK ,  Byung-Hee KIM ,  Sang-Hoon AHN ,  Kwang-Jin MOON

发明人： Kyoung-Hee KIM ,  Gil-Heyun CHOI ,  Kyu-Hee HAN ,  Byung-Lyul PARK ,  Byung-Hee KIM ,  Sang-Hoon AHN ,  Kwang-Jin MOON

IPC分类号： H01L23/48 ,  H01L21/768

CPC分类号： H01L21/76898 ,  H01L21/7682 ,  H01L21/76831 ,  H01L23/3171 ,  H01L23/481 ,  H01L24/05 ,  H01L24/45 ,  H01L24/48 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05009 ,  H01L2224/06181 ,  H01L2224/13022 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/451 ,  H01L2224/48245 ,  H01L2224/48247 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06544 ,  H01L2225/06565 ,  H01L2924/00013 ,  H01L2924/01327 ,  H01L2224/13099 ,  H01L2224/05099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/00 ,  H01L2924/00014

摘要： A semiconductor device comprises a top surface having a first contact, a bottom surface having a second contact, a via hole penetrating a substrate, an insulation layer structure on a sidewall of the via hole, the insulation layer structure having an air gap therein, a through electrode having an upper surface and a lower surface on the insulation layer structure, the through electrode filling the via hole and the lower surface being the second contact, and a metal wiring electrically connected to the upper surface of the through electrode and electrically connected to the first contact.

摘要翻译： 半导体器件包括具有第一触点的顶表面，具有第二触点的底表面，穿透基板的通孔，在通孔的侧壁上的绝缘层结构，其中具有气隙的绝缘层结构， 所述贯通电极在所述绝缘层结构上具有上表面和下表面，所述贯通电极填充所述通孔，所述下表面是所述第二接触，以及金属布线，电连接到所述通孔的上表面，并电连接到 第一次接触。

公开(公告)号：US20120282736A1

公开(公告)日：2012-11-08

申请号：US13459468

申请日：2012-04-30

申请人： Kwang-Jin MOON ,  Byung-Lyul PARK ,  Do-Sun LEE ,  Gil-Heyun CHOI ,  Suk-Chul BANG ,  Dong-Chan LIM ,  Deok-Young JUNG

发明人： Kwang-Jin MOON ,  Byung-Lyul PARK ,  Do-Sun LEE ,  Gil-Heyun CHOI ,  Suk-Chul BANG ,  Dong-Chan LIM ,  Deok-Young JUNG

IPC分类号： H01L21/50 ,  H01L21/768

CPC分类号： H01L21/2885 ,  H01L21/76898 ,  H01L25/0657 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/15311

摘要： In a method of manufacturing a semiconductor device, a front end of line (FEOL) process may be performed on a semiconductor substrate to form a semiconductor structure. A back end of line (BEOL) process may be performed on the semiconductor substrate to form a wiring structure electrically connected to the semiconductor structure, thereby formed a semiconductor chip. A hole may be formed through a part of the semiconductor chip. A preliminary plug may have a dimple in the hole. The preliminary plug may be expanded into the dimple by a thermal treatment process to form a plug. Thus, the plug may not have a protrusion protruding from the upper surface of the semiconductor chip, so that the plug may be formed by the single CMP process.

摘要翻译： 在制造半导体器件的方法中，可以在半导体衬底上执行前端（FEOL）工艺以形成半导体结构。 可以在半导体基板上进行后端（BEOL）处理，以形成与半导体结构电连接的布线结构，从而形成半导体芯片。 可以通过半导体芯片的一部分形成孔。 初步插头可能在孔中有一个凹坑。 预先塞子可以通过热处理过程扩展到凹坑中以形成塞子。 因此，插头可以不具有从半导体芯片的上表面突出的突起，从而可以通过单个CMP工艺形成插头。

公开(公告)号：US20130062719A1

公开(公告)日：2013-03-14

申请号：US13614730

申请日：2012-09-13

申请人： Pil-Kyu KANG ,  Joong-Han SHIN ,  Byung-Lyul PARK ,  Gil-Heyun CHOI

发明人： Pil-Kyu KANG ,  Joong-Han SHIN ,  Byung-Lyul PARK ,  Gil-Heyun CHOI

IPC分类号： H01L31/0232

CPC分类号： G02B6/4206 ,  G02B6/12004 ,  G02B6/42 ,  G02B6/4201 ,  G02B6/4204 ,  H01L31/0232

摘要： An optical input/output (I/O) device is provided. The device includes a substrate including an upper trench; a waveguide disposed within the upper trench of the substrate; a photodetector disposed within the upper trench of the substrate and comprising a first end surface optically connected to an end surface of the waveguide; and a light-transmitting insulating layer interposed between the end surface of the waveguide and the first end surface of the photodetector.

摘要翻译： 提供光输入/输出（I / O）设备。 该装置包括：包括上沟槽的衬底; 布置在所述衬底的上沟槽内的波导; 光电检测器，设置在所述衬底的上沟槽内，并且包括光学连接到所述波导的端面的第一端面; 以及插入在波导的端面与光检测器的第一端面之间的透光绝缘层。

公开(公告)号：US20130200525A1

公开(公告)日：2013-08-08

申请号：US13718580

申请日：2012-12-18

申请人： Ho-Jin LEE ,  Pil-Kyu KANG ,  Kyu-Ha LEE ,  Byung-Lyul PARK ,  Hyun-Soo CHUNG ,  Gil-Heyun CHOI

发明人： Ho-Jin LEE ,  Pil-Kyu KANG ,  Kyu-Ha LEE ,  Byung-Lyul PARK ,  Hyun-Soo CHUNG ,  Gil-Heyun CHOI

IPC分类号： H01L23/48

CPC分类号： H01L23/481 ,  H01L21/76898 ,  H01L23/525 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05 ,  H01L2224/05024 ,  H01L2224/05027 ,  H01L2224/05568 ,  H01L2224/06181 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2924/00014 ,  H01L2924/13091 ,  H01L2924/00 ,  H01L2224/05552

摘要： A semiconductor device including a lower layer, an insulating layer on a first side of the lower layer, an interconnection structure in the insulating layer, a via structure in the lower layer. The via structure protrudes into the insulating layer and the interconnection structure.

摘要翻译： 一种半导体器件，包括下层，在下层的第一侧上的绝缘层，绝缘层中的互连结构，下层中的通孔结构。 通孔结构突出到绝缘层和互连结构中。

公开(公告)号：US20100184294A1

公开(公告)日：2010-07-22

申请号：US12687987

申请日：2010-01-15

申请人： Jin-Ho Park ,  Gil-Heyun CHOI ,  Byung-Lyul PARK ,  Jong-Myeong LEE ,  Zung-Sun CHOI ,  Hye-Kyung JUNG

发明人： Jin-Ho Park ,  Gil-Heyun CHOI ,  Byung-Lyul PARK ,  Jong-Myeong LEE ,  Zung-Sun CHOI ,  Hye-Kyung JUNG

IPC分类号： H01L21/311 ,  B08B7/00

CPC分类号： H01L21/6719 ,  H01L21/28556 ,  H01L21/28562 ,  H01L21/76843 ,  H01L21/76856 ,  H01L21/76861 ,  H01L21/76877

摘要： In a method of manufacturing a semiconductor device, a substrate is loaded to a process chamber having, unit process sections in which unit processes are performed, respectively. The unit processes are performed on the substrate independently from one another at the unit process sections under a respective process pressure. The substrate sequentially undergoes the unit processes at the respective unit process section of the process chamber. Cleaning processes are individually performed to the unit process sections, respectively, when the substrate is transferred from each of the unit process sections and no substrate is positioned at the unit process sections. Accordingly, the process defects of the process units may be sufficiently prevented and the operation period of the manufacturing apparatus is sufficiently elongated.

摘要翻译： 在制造半导体器件的方法中，将衬底装载到具有分别执行单元处理的单元处理部的处理室。 单元处理在相应的处理压力下在单元处理部分彼此独立地在衬底上进行。 基板在处理室的各单元处理部分依次进行单元处理。 当从每个单元处理部分传送基板并且没有基板位于单元处理部分时，分别对单元处理部分进行清洁处理。 因此，可以充分防止处理单元的处理缺陷，并且制造装置的操作周期充分延长。

公开(公告)号：US20110003455A1

公开(公告)日：2011-01-06

申请号：US12801115

申请日：2010-05-24

申请人： Woong-Hee SOHN ,  Gil-Heyun CHOI ,  Byung-Hee KIM ,  Byung-Hak LEE ,  Tae-Ho CHA ,  Hee-Sook PARK ,  Jae-Hwa PARK ,  Geum-Jung SEONG

发明人： Woong-Hee SOHN ,  Gil-Heyun CHOI ,  Byung-Hee KIM ,  Byung-Hak LEE ,  Tae-Ho CHA ,  Hee-Sook PARK ,  Jae-Hwa PARK ,  Geum-Jung SEONG

IPC分类号： H01L21/336 ,  H01L21/76

CPC分类号： H01L21/823481 ,  H01L21/28202 ,  H01L21/28211 ,  H01L21/2822 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/78 ,  Y10S438/981

摘要： Disclosed are a variety of methods for increasing the relative thickness in the peripheral or edge regions of gate dielectric patterns to suppress leakage through these regions. The methods provide alternatives to conventional GPDX processes and provide the improved leakage resistance without incurring the degree of increased gate electrode resistance associated with GPDX processes. Each of the methods includes forming a first opening to expose an active area region, forming an oxidation control region on the exposed portion and then forming a second opening whereby a peripheral region free of the oxidation control region is exposed for formation of a gate dielectric layer. The resulting gate dielectric layers are characterized by a thinner central region surrounded or bounded by a thicker peripheral region.

摘要翻译： 公开了用于增加栅极电介质图案的外围或边缘区域中的相对厚度以抑制这些区域的泄漏的各种方法。 这些方法提供了常规GPDX工艺的替代方案，并提供改进的耐漏电性，而不会导致与GPDX工艺相关的增加的栅电极电阻的程度。 每种方法包括形成第一开口以暴露有源区域区域，在暴露部分上形成氧化控制区域，然后形成第二开口，由此暴露氧化控制区域的外围区域以形成栅极介电层 。 得到的栅极介电层的特征在于由较厚的外围区域包围或界定的较薄的中心区域。

公开(公告)号：US20080102615A1

公开(公告)日：2008-05-01

申请号：US11685644

申请日：2007-03-13

申请人： Byung-Hak LEE ,  Woong-Hee SOHN ,  Jae-Hwa PARK ,  Gil-Heyun CHOI ,  Byung-Hee KIM ,  Hee-Sook PARK

发明人： Byung-Hak LEE ,  Woong-Hee SOHN ,  Jae-Hwa PARK ,  Gil-Heyun CHOI ,  Byung-Hee KIM ,  Hee-Sook PARK

IPC分类号： H01L21/4763

CPC分类号： H01L21/28282 ,  H01L27/105 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11568

摘要： One embodiment of a method for forming a semiconductor device can include forming a gate pattern on a semiconductor substrate and performing a selective re-oxidation process on the gate pattern in gas ambient including hydrogen, oxygen, and nitrogen. When the gate pattern includes a tunnel insulation layer, a metal nitride layer and a metal layer, the selective re-oxidation process heals the etching damage of a gate pattern and simultaneously prevents oxidation of the metal nitride layer and a tungsten electrode.

摘要翻译： 用于形成半导体器件的方法的一个实施例可以包括在半导体衬底上形成栅极图案，并且在包括氢，氧和氮在内的气体环境中对栅极图案进行选择性再氧化处理。 当栅极图案包括隧道绝缘层，金属氮化物层和金属层时，选择性再氧化工艺会修复栅极图案的蚀刻损伤，同时防止金属氮化物层和钨电极的氧化。

公开(公告)号：US20110223725A1

公开(公告)日：2011-09-15

申请号：US13044703

申请日：2011-03-10

申请人： Pil-Kyu KANG ,  Dae-Lok BAE ,  Gil-Heyun CHOI ,  Jong-Myeong LEE

发明人： Pil-Kyu KANG ,  Dae-Lok BAE ,  Gil-Heyun CHOI ,  Jong-Myeong LEE

IPC分类号： H01L21/336 ,  H01L21/762

CPC分类号： H01L21/76254 ,  H01L21/743 ,  H01L21/84 ,  H01L27/10817 ,  H01L27/10855 ,  H01L27/10876 ,  H01L27/10885 ,  H01L27/10894 ,  H01L27/1203

摘要： A method of manufacturing a buried wiring type substrate comprises implanting hydrogen ions into a single crystalline substrate through a first surface thereof to form an ion implantation region, forming a conductive layer comprising a metal on the first surface of the single crystalline substrate, forming an insulation layer comprising silicon oxide on the conductive layer, bonding the insulation layer to a support substrate to form a preliminary buried wiring type substrate, and separating the single crystalline substrate at the ion implantation region to form a single crystalline semiconductor layer on the conductive layer.

摘要翻译： 一种掩埋布线型衬底的制造方法，包括通过其第一表面将氢离子注入单晶衬底以形成离子注入区，在单晶衬底的第一表面上形成包含金属的导电层，形成绝缘层 在导电层上包含氧化硅的层，将绝缘层粘合到支撑衬底上以形成预埋掩埋布线型衬底，并且在离子注入区域处分离单晶衬底，以在导电层上形成单晶半导体层。

公开(公告)号：US20060234494A1

公开(公告)日：2006-10-19

申请号：US11425970

申请日：2006-06-22

申请人： Kyung-In CHOI ,  Sang-Bom KANG ,  Seong-Geon PARK ,  You-Kyoung LEE ,  Gil-Heyun CHOI ,  Jong-Myeong LEE ,  Sang-Woo LEE

发明人： Kyung-In CHOI ,  Sang-Bom KANG ,  Seong-Geon PARK ,  You-Kyoung LEE ,  Gil-Heyun CHOI ,  Jong-Myeong LEE ,  Sang-Woo LEE

IPC分类号： H01L21/4763

CPC分类号： H01L21/28556 ,  C23C16/34 ,  C23C16/45553 ,  H01L21/28562 ,  H01L21/76843 ,  H01L21/7685 ,  H01L21/76858 ,  H01L21/76862 ,  H01L21/76867 ,  H01L21/76877

摘要： In a method for forming a wiring of a semiconductor device using an atomic layer deposition, an insulating interlayer is formed on a substrate. Tantalum amine derivatives represented by a chemical formula Ta(NR1)(NR2R3)3 in which R1, R2 and R3 represent H or C1-C6 alkyl group are introduced onto the insulating interlayer. A portion of the tantalum amine derivatives is chemisorbed on the insulating interlayer. The rest of tantalum amine derivatives non-chemisorbed on the insulating interlayer is removed from the insulating interlayer. A reacting gas is introduced onto the insulating interlayer. A ligand in the tantalum amine derivatives chemisorbed on the insulating interlayer is removed from the tantalum amine derivatives by a chemical reaction between the reacting gas and the ligand to form a solid material including tantalum nitride. The solid material is accumulated on the insulating interlayer through repeating the above processes to form a wiring.

摘要翻译： 在使用原子层沉积形成半导体器件的布线的方法中，在基板上形成绝缘中间层。 由化学式Ta（NR 1）3（NR 2 R 3）3表示的钽胺衍生物，其中 R 1，R 2和R 3代表H或C 1 -C 6 >烷基引入到绝缘中间层上。 一部分钽胺衍生物被化学吸附在绝缘中间层上。 在绝缘中间层上除去非化学吸附在绝缘中间层上的其余的钽胺衍生物。 将反应气体引入到绝缘中间层上。 化学吸附在绝缘中间层上的钽胺衍生物中的配体通过反应气体和配位体之间的化学反应从钽胺衍生物中除去以形成包括氮化钽的固体材料。 通过重复上述处理，将固体材料积聚在绝缘层间，形成布线。

公开(公告)号：US20090256177A1

公开(公告)日：2009-10-15

申请号：US12453198

申请日：2009-05-01

申请人： Hee-Sook PARK ,  Gil-Heyun CHOI ,  Chang-Won LEE ,  Byung-Hak LEE ,  Sun-Pil YOUN ,  Dong-Chan LIM ,  Jae-Hwa PARK ,  Jang-Hee LEE ,  Woong-Hee SOHN

发明人： Hee-Sook PARK ,  Gil-Heyun CHOI ,  Chang-Won LEE ,  Byung-Hak LEE ,  Sun-Pil YOUN ,  Dong-Chan LIM ,  Jae-Hwa PARK ,  Jang-Hee LEE ,  Woong-Hee SOHN

IPC分类号： H01L29/80 ,  H01L23/498 ,  H01L23/52

CPC分类号： H01L29/4933 ,  C23C16/42 ,  H01L21/28061 ,  H01L21/28194 ,  H01L21/28556 ,  H01L21/76846 ,  H01L29/517

摘要： In an ohmic layer and methods of forming the ohmic layer, a gate structure including the ohmic layer and a metal wiring having the ohmic layer, the ohmic layer is formed using tungsten silicide that includes tungsten and silicon with an atomic ratio within a range of about 1:5 to about 1:15. The tungsten silicide may be obtained in a chamber using a reaction gas including a tungsten source gas and a silicon source gas by a partial pressure ratio within a range of about 1.0:25.0 to about 1.0:160.0. The reaction gas may have a partial pressure within a range of about 2.05 percent to about 30.0 percent of a total internal pressure of the chamber. When the ohmic layer is employed for a conductive structure, such as a gate structure or a metal wiring, the conductive structure may have a reduced resistance.

摘要翻译： 在欧姆层和形成欧姆层的方法中，包括欧姆层的栅极结构和具有欧姆层的金属布线，欧姆层使用包含钨和硅的钨硅化物形成，原子比在约 1:5至约1:15。 可以在室内使用包含钨源气体和硅源气体的反应气体，在约1.0:25.0至约1.0:16.0.0的范围内的分压比获得硅化钨。 反应气体可以具有在室的总内部压力的约2.05％至约30.0％的范围内的分压。 当欧姆层用于诸如栅极结构或金属布线的导电结构时，导电结构可以具有降低的电阻。