VERTICAL NAND FLASH MEMORY DEVICE
    1.
    发明申请
    VERTICAL NAND FLASH MEMORY DEVICE 有权
    垂直NAND闪存存储器件

    公开(公告)号:US20160343727A1

    公开(公告)日:2016-11-24

    申请号:US14992154

    申请日:2016-01-11

    IPC分类号: H01L27/115 H01L23/528

    摘要: Provided is a vertical NAND flash memory device. The vertical NAND flash memory device may include word lines formed on a substrate, a plurality of pads horizontally extending from the word lines, and contact plugs connected to respective pads. The contact plugs may include a first contact plug connected to a lowermost pad that is closest to the substrate, and a set of second contact plugs each second contact plug connected to a corresponding pad of the plurality of pads. A first distance between the first contact plug and a second contact plug of the set of second contact plugs that is adjacent to the first contact plug may be different from second distances between adjacent contact plugs of the set of second contact plugs. The second distances may be substantially the same as each other.

    摘要翻译: 提供了一种垂直NAND闪存设备。 垂直NAND闪存器件可以包括形成在基板上的字线,从字线水平延伸的多个焊盘以及连接到相应焊盘的接触插头。 接触插塞可以包括连接到最靠近衬底的最下垫的第一接触插塞和一组第二接触插塞,每个第二接触插塞连接到多个衬垫的相应衬垫。 所述第一接触插塞和与所述第一接触插塞相邻的所述一组第二接触插塞的第二接触插塞之间的第一距离可以不同于所述一组第二接触插塞的相邻接触插塞之间的第二距离。 第二距离可以彼此基本相同。

    SEMICONDUCTOR MEMORY DEVICES HAVING VERTICAL PILLARS THAT ARE ELECTRICALLY CONNECTED TO LOWER CONTACTS
    2.
    发明申请
    SEMICONDUCTOR MEMORY DEVICES HAVING VERTICAL PILLARS THAT ARE ELECTRICALLY CONNECTED TO LOWER CONTACTS 有权
    具有电气连接到下降触点的垂直支架的半导体存储器件

    公开(公告)号:US20170040336A1

    公开(公告)日:2017-02-09

    申请号:US14963280

    申请日:2015-12-09

    IPC分类号: H01L27/115

    CPC分类号: H01L27/11582 H01L28/00

    摘要: A semiconductor memory device may include an electrode structure including a selection line on a substrate and word lines between the substrate and the selection line, vertical pillars penetrating the electrode structure and being connected to the substrate, sub-interconnections and bit lines sequentially stacked on and electrically connected to the vertical pillars, and lower contacts connecting the vertical pillars to the sub-interconnections. The selection line may include a plurality of selection lines separated from each other in a first direction by an insulating separation layer, and central axes of the lower contacts connected in common to one of the sub-interconnections may be shifted, in a second direction across the first direction and parallel to a top surface of the substrate, from central axes of the vertical pillars thereunder.

    摘要翻译: 半导体存储器件可以包括:电极结构,其包括在衬底上的选择线和衬底与选择线之间的字线,穿过电极结构的垂直柱和连接到衬底,顺序堆叠在衬底上的子互连和位线 电连接到垂直柱,以及将垂直柱连接到副互连的下触点。 选择线可以包括通过绝缘分离层在第一方向上彼此分离的多条选择线,并且共同连接到一个子互连的下触点的中心轴可以沿着第二方向跨越 第一方向并平行于基板的顶表面,从其垂直柱的中心轴线。