公开(公告)号：US20050029010A1

公开(公告)日：2005-02-10

申请号：US10891062

申请日：2004-07-15

申请人： Jeong-hoon Ahn ,  Hyo-jong Lee ,  Kyung-tae Lee ,  Kyoung-woo Lee ,  Soo-geun Lee ,  Bong-seok Suh

发明人： Jeong-hoon Ahn ,  Hyo-jong Lee ,  Kyung-tae Lee ,  Kyoung-woo Lee ,  Soo-geun Lee ,  Bong-seok Suh

IPC分类号： H01L21/768 ,  H01L21/28 ,  H01L21/3205 ,  H01L21/4763 ,  H01L23/52 ,  H05K1/11

CPC分类号： H01L21/76877 ,  H01L21/76847

摘要： A metal interconnection structure includes a lower metal interconnection layer disposed in a first inter-layer dielectric layer. An inter-metal dielectric layer having a via contact hole that exposes a portion of surface of the lower metal layer pattern is disposed on the first inter-layer dielectric layer and the lower metal layer pattern. A second inter-layer dielectric layer having a trench that exposes the via contact hole is formed on the inter-metal dielectric layer. A barrier metal layer is formed on a vertical surface of the via contact and the exposed surface of the second lower metal interconnection layer pattern. A first upper metal interconnection layer pattern is disposed on the barrier metal layer, thereby filling the via contact hole and a portion of the trench. A void diffusion barrier layer is disposed on the first metal interconnection layer pattern and a second upper metal interconnection layer pattern is disposed on the void diffusion barrier layer to completely fill the trench.

摘要翻译： 金属互连结构包括设置在第一层间电介质层中的下金属互连层。 具有暴露下部金属层图案的一部分表面的通孔接触孔的金属间介电层设置在第一层间电介质层和下部金属层图案上。 在金属间电介质层上形成具有暴露通孔接触孔的沟槽的第二层间电介质层。 在通孔接触件的垂直表面和第二下部金属互连层图案的暴露表面上形成阻挡金属层。 第一上金属互连层图案设置在阻挡金属层上，从而填充通孔接触孔和沟槽的一部分。 空隙扩散阻挡层设置在第一金属互连层图案上，并且第二上金属互连层图案设置在空隙扩散阻挡层上以完全填充沟槽。

公开(公告)号：US06828229B2

公开(公告)日：2004-12-07

申请号：US10081661

申请日：2002-02-22

申请人： Soo-geun Lee ,  Hong-jae Shin ,  Kyoung-woo Lee ,  Jae-hak Kim

发明人： Soo-geun Lee ,  Hong-jae Shin ,  Kyoung-woo Lee ,  Jae-hak Kim

IPC分类号： H01L214763

CPC分类号： H01L21/76808 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31144

摘要： A method of forming an interconnection line in a semiconductor device is provided. A first etching stopper is formed on a lower conductive layer which is formed on a semiconductor substrate. A first interlayer insulating layer is formed on the first etching stopper. A second etching stopper is formed on the first interlayer insulating layer. A second interlayer insulating layer is formed on the second etching stopper. The second interlayer insulating layer, the second etching stopper, and the first interlayer insulating layer are sequentially etched using the first etching stopper as an etching stopping point to form a via hole aligned with the lower conductive layer. A protective layer is formed to protect a portion of the first etching stopper exposed at the bottom of the via hole. A portion of the second interlayer insulating layer adjacent to the via hole is etched using the second etching stopper as an etching stopping point to form a trench connected to the via hole. The protective layer is removed. The portion of the first etching stopper positioned at the bottom of the via hole is removed. An upper conductive layer that fills the via hole and the trench and is electrically connected to the lower conductive layer is formed.

摘要翻译： 提供了一种在半导体器件中形成互连线的方法。 在形成在半导体衬底上的下导电层上形成第一蚀刻阻挡层。 在第一蚀刻停止件上形成第一层间绝缘层。 在第一层间绝缘层上形成第二蚀刻阻挡层。 在第二蚀刻停止件上形成第二层间绝缘层。 使用第一蚀刻停止器作为蚀刻停止点，依次蚀刻第二层间绝缘层，第二蚀刻停止层和第一层间绝缘层，以形成与下导电层对准的通孔。 形成保护层以保护暴露在通孔底部的第一蚀刻终止部分。 使用第二蚀刻停止器蚀刻与通孔相邻的第二层间绝缘层的一部分作为蚀刻停止点，以形成连接到通孔的沟槽。 保护层被去除。 位于通孔底部的第一蚀刻停止部分被去除。 形成填充通孔和沟槽并与下导电层电连接的上导电层。

公开(公告)号：US20070184610A1

公开(公告)日：2007-08-09

申请号：US11733711

申请日：2007-04-10

申请人： Kyoung-woo Lee ,  Wan-jae Park ,  Jeong-hoon Ahn ,  Kyung-tae Lee ,  Mu-kyeng Jung ,  Yong-jun Lee ,  Il-goo Kim ,  Soo-geun Lee

发明人： Kyoung-woo Lee ,  Wan-jae Park ,  Jeong-hoon Ahn ,  Kyung-tae Lee ,  Mu-kyeng Jung ,  Yong-jun Lee ,  Il-goo Kim ,  Soo-geun Lee

IPC分类号： H01L21/8242 ,  H01L21/20

CPC分类号： H01L28/40 ,  H01L23/5222 ,  H01L2924/0002 ,  H01L2924/00

摘要： Embodiments of the invention include a MIM capacitor that has a high capacitance that can be manufactured without the problems that affected the prior art. Such a capacitor includes an upper electrode, a lower electrode, and a dielectric layer that is intermediate the upper and the lower electrodes. A first voltage can be applied to the upper electrode and a second voltage, which is different from the first voltage, can be applied to the lower electrode. A wire layer, through which the first voltage is applied to the upper electrode, is located in the same level as or in a lower level than the lower electrode.

公开(公告)号：US07605472B2

公开(公告)日：2009-10-20

申请号：US11706885

申请日：2007-02-15

申请人： Kyoung-woo Lee ,  Soo-geun Lee ,  Ki-chul Park ,  Won-sang Song

发明人： Kyoung-woo Lee ,  Soo-geun Lee ,  Ki-chul Park ,  Won-sang Song

IPC分类号： H01L29/40

CPC分类号： H01L21/76832 ,  H01L21/76807 ,  H01L21/76834 ,  H01L21/76843 ,  H01L21/76873 ,  H01L21/76874 ,  H01L21/76877 ,  H01L21/76883 ,  H01L23/53228 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： Provided are an interconnection of a semiconductor device which includes a capping layer and a method for forming the interconnection. The interconnection of the semiconductor device is a copper damascene interconnection where the capping layer is formed as a dual layer of a silicon nitride layer and silicon carbide layer on a copper layer processed by chemical mechanical polishing (CMP). Therefore, it is possible to maintain a high etching selectivity and a low dielectric constant of the silicon carbide layer while providing superior leakage suppression.

摘要翻译： 提供了包括封盖层和形成互连的方法的半导体器件的互连。 半导体器件的互连是铜镶嵌互连，其中覆盖层形成为通过化学机械抛光（CMP）处理的铜层上的氮化硅层和碳化硅层的双层。 因此，可以在提供优异的泄漏抑制的同时保持碳化硅层的高蚀刻选择性和低介电常数。

公开(公告)号：US07279733B2

公开(公告)日：2007-10-09

申请号：US10799292

申请日：2004-03-12

申请人： Kyoung-woo Lee ,  Soo-geun Lee

发明人： Kyoung-woo Lee ,  Soo-geun Lee

IPC分类号： H01L27/108 ,  H01L29/94

CPC分类号： H01L21/76807 ,  H01L23/5223 ,  H01L28/55 ,  H01L2924/0002 ,  H01L2924/00

摘要： Provided are a dual damascene interconnection with a metal-insulator-metal (MIM) capacitor and a method of fabricating the same. In this structure, an MIM capacitor is formed on a via-level IMD. After the via-level IMD is formed, while an alignment key used for patterning the MIM capacitor is being formed, a via hole is formed to connect a lower electrode of the MIM capacitor and an interconnection disposed under the via-level IMD. Also, an upper electrode of the MIM capacitor is directly connected to an upper metal interconnection during a dual damascene process.

摘要翻译： 提供了一种与金属 - 绝缘体 - 金属（MIM）电容器的双镶嵌互连及其制造方法。 在该结构中，在通孔级IMD上形成MIM电容器。 在形成通孔级IMD之后，当形成MIM电容器图形化的对准键时，形成通孔，以连接MIM电容器的下电极和配置在通孔级IMD下的互连。 此外，在双镶嵌工艺期间，MIM电容器的上电极直接连接到上金属互连。

公开(公告)号：US20070138642A1

公开(公告)日：2007-06-21

申请号：US11706885

申请日：2007-02-15

申请人： Kyoung-woo Lee ,  Soo-geun Lee ,  Ki-chul Park ,  Won-sang Song

发明人： Kyoung-woo Lee ,  Soo-geun Lee ,  Ki-chul Park ,  Won-sang Song

IPC分类号： H01L23/52 ,  H01L23/48

CPC分类号： H01L21/76832 ,  H01L21/76807 ,  H01L21/76834 ,  H01L21/76843 ,  H01L21/76873 ,  H01L21/76874 ,  H01L21/76877 ,  H01L21/76883 ,  H01L23/53228 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： Provided are an interconnection of a semiconductor device which includes a capping layer and a method for forming the interconnection. The interconnection of the semiconductor device is a copper damascene interconnection where the capping layer is formed as a dual layer of a silicon nitride layer and silicon carbide layer on a copper layer processed by chemical mechanical polishing (CMP). Therefore, it is possible to maintain a high etching selectivity and a low dielectric constant of the silicon carbide layer while providing superior leakage suppression.

摘要翻译： 提供了包括封盖层和形成互连的方法的半导体器件的互连。 半导体器件的互连是铜镶嵌互连，其中覆盖层形成为通过化学机械抛光（CMP）处理的铜层上的氮化硅层和碳化硅层的双层。 因此，可以在提供优异的泄漏抑制的同时保持碳化硅层的高蚀刻选择性和低介电常数。

公开(公告)号：US07205666B2

公开(公告)日：2007-04-17

申请号：US11367790

申请日：2006-03-03

申请人： Kyoung-woo Lee ,  Soo-geun Lee ,  Ki-chul Park ,  Won-sang Song

发明人： Kyoung-woo Lee ,  Soo-geun Lee ,  Ki-chul Park ,  Won-sang Song

IPC分类号： H01L29/40

CPC分类号： H01L21/76832 ,  H01L21/76807 ,  H01L21/76834 ,  H01L21/76843 ,  H01L21/76873 ,  H01L21/76874 ,  H01L21/76877 ,  H01L21/76883 ,  H01L23/53228 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： Provided are an interconnection of a semiconductor device which includes a capping layer and a method for forming the interconnection. The interconnection of the semiconductor device is a copper damascene interconnection where the capping layer is formed as a dual layer of a silicon nitride layer and silicon carbide layer on a copper layer processed by chemical mechanical polishing (CMP). Therefore, it is possible to maintain a high etching selectivity and a low dielectric constant of the silicon carbide layer while providing superior leakage suppression.

公开(公告)号：US07951712B2

公开(公告)日：2011-05-31

申请号：US12556094

申请日：2009-09-09

申请人： Kyoung-woo Lee ,  Soo-geun Lee ,  Ki-chul Park ,  Won-sang Song

发明人： Kyoung-woo Lee ,  Soo-geun Lee ,  Ki-chul Park ,  Won-sang Song

IPC分类号： H01L21/44

CPC分类号： H01L21/76832 ,  H01L21/76807 ,  H01L21/76834 ,  H01L21/76843 ,  H01L21/76873 ,  H01L21/76874 ,  H01L21/76877 ,  H01L21/76883 ,  H01L23/53228 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： Provided are an interconnection of a semiconductor device which includes a capping layer and a method for forming the interconnection. The interconnection of the semiconductor device is a copper damascene interconnection where the capping layer is formed as a dual layer of a silicon nitride layer and silicon carbide layer on a copper layer processed by chemical mechanical polishing (CMP). Therefore, it is possible to maintain a high etching selectivity and a low dielectric constant of the silicon carbide layer while providing superior leakage suppression.

摘要翻译： 提供了包括封盖层和形成互连的方法的半导体器件的互连。 半导体器件的互连是铜镶嵌互连，其中覆盖层形成为通过化学机械抛光（CMP）处理的铜层上的氮化硅层和碳化硅层的双层。 因此，可以在提供优异的泄漏抑制的同时保持碳化硅层的高蚀刻选择性和低介电常数。

公开(公告)号：US20100003814A1

公开(公告)日：2010-01-07

申请号：US12556094

申请日：2009-09-09

申请人： Kyoung-woo Lee ,  Soo-geun Lee ,  Ki-chul Park ,  Won-sang Song

发明人： Kyoung-woo Lee ,  Soo-geun Lee ,  Ki-chul Park ,  Won-sang Song

IPC分类号： H01L21/768

CPC分类号： H01L21/76832 ,  H01L21/76807 ,  H01L21/76834 ,  H01L21/76843 ,  H01L21/76873 ,  H01L21/76874 ,  H01L21/76877 ,  H01L21/76883 ,  H01L23/53228 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： Provided are an interconnection of a semiconductor device which includes a capping layer and a method for forming the interconnection. The interconnection of the semiconductor device is a copper damascene interconnection where the capping layer is formed as a dual layer of a silicon nitride layer and silicon carbide layer on a copper layer processed by chemical mechanical polishing (CMP). Therefore, it is possible to maintain a high etching selectivity and a low dielectric constant of the silicon carbide layer while providing superior leakage suppression.

摘要翻译： 提供了包括封盖层和形成互连的方法的半导体器件的互连。 半导体器件的互连是铜镶嵌互连，其中覆盖层形成为通过化学机械抛光（CMP）处理的铜层上的氮化硅层和碳化硅层的双层。 因此，可以在提供优异的泄漏抑制的同时保持碳化硅层的高蚀刻选择性和低介电常数。

公开(公告)号：US07399700B2

公开(公告)日：2008-07-15

申请号：US11897417

申请日：2007-08-30

申请人： Kyoung-woo Lee ,  Soo-geun Lee

发明人： Kyoung-woo Lee ,  Soo-geun Lee

IPC分类号： H01L21/4763

CPC分类号： H01L21/76807 ,  H01L23/5223 ,  H01L28/55 ,  H01L2924/0002 ,  H01L2924/00

摘要： Provided are a dual damascene interconnection with a metal-insulator-metal (MIM) capacitor and a method of fabricating the same. In this structure, an MIM capacitor is formed on a via-level IMD. After the via-level IMD is formed, while an alignment key used for patterning the MIM capacitor is being formed, a via hole is formed to connect a lower electrode of the MIM capacitor and an interconnection disposed under the via-level IMD. Also, an upper electrode of the MIM capacitor is directly connected to an upper metal interconnection during a dual damascene process.

摘要翻译： 提供了一种与金属 - 绝缘体 - 金属（MIM）电容器的双镶嵌互连及其制造方法。 在该结构中，在通孔级IMD上形成MIM电容器。 在形成通孔级IMD之后，当形成MIM电容器图形化的对准键时，形成通孔，以连接MIM电容器的下电极和配置在通孔级IMD下的互连。 此外，在双镶嵌工艺期间，MIM电容器的上电极直接连接到上金属互连。