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公开(公告)号：US5892386A
公开(公告)日：1999-04-06
申请号：US760250
申请日：1996-12-05
申请人： Kyu-chan Lee , Jung-hwa Lee , Seung-moon Yoo
发明人： Kyu-chan Lee , Jung-hwa Lee , Seung-moon Yoo
IPC分类号： G11C11/401 , G11C5/14 , G11C29/04 , G11C29/50 , H01L21/822 , H01L27/04 , H03K3/037
CPC分类号： G11C29/50 , G11C11/401
摘要： An internal power control circuit for a semiconductor device allows easy testing of the internal circuit blocks or memory arrays at various voltage levels. In the semiconductor device, internal voltage switching circuits connected between the internal power supply line and each array power supply line are switched ON or OFF according to signals applied to control pads coupled to each internal voltage switching circuit. During normal operation, a power voltage generated by the internal voltage generator is applied through an internal power supply line to each array power supply line coupled to the internal circuit blocks. During a test operation, different power voltages may be applied to the control pads to selectively decouple individual array power supply lines from the internal power supply line, and selectively couple the power voltages applied to the control pads to the corresponding array power supply lines and internal circuit blocks.
摘要翻译： 用于半导体器件的内部功率控制电路允许在各种电压电平下容易地测试内部电路块或存储器阵列。 在半导体器件中，连接在内部电源线和每个阵列电源线之间的内部电压切换电路根据施加到耦合到每个内部电压切换电路的控制焊盘的信号而被接通或断开。 在正常操作期间，内部电压发生器产生的电力电压通过内部电源线施加到耦合到内部电路块的每个阵列电源线。 在测试操作期间，可以将不同的电源电压施加到控制焊盘，以选择性地将各个阵列电源线与内部电源线分离，并且将施加到控制焊盘的电力电压选择性地耦合到相应的阵列电源线和内部 电路块。
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公开(公告)号：US20060171477A1
公开(公告)日：2006-08-03
申请号：US11050605
申请日：2005-02-03
申请人： Juan-Antonio Carballo , Kevin Nowka , Ivan Vo , Seung-moon Yoo
发明人： Juan-Antonio Carballo , Kevin Nowka , Ivan Vo , Seung-moon Yoo
IPC分类号： H04L25/00
CPC分类号： H04L25/028 , H04L25/0272 , H04L25/0292
摘要： A digital transmission circuit and method providing selectable power consumption via single-ended or differential operation improves the flexibility of an interface while reducing power consumption when possible. A differential path is provided through the transmitter output driver stages and portions are selectively disabled when the transmission circuit is in a lower-power operating mode. A single-ended to differential converter circuit can be used to construct a differential signal for output to the final driver stage. The selection of power mode can be made via feedback from a channel quality measurement unit or may be hardwired or selected under programmatic control. The longer delay or skew of the lower-power single-ended mode is compensated for by the relaxed requirements of the channel when conditions permit the use of the lower-power single-ended mode.
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3.发明授权Digital transmission circuit and method providing selectable power consumption via multiple weighted driver slices 有权数字传输电路和方法通过多个加权驱动器片提供可选择的功耗公开(公告)号：US07636556B2
公开(公告)日：2009-12-22
申请号：US12015458
申请日：2008-01-16
IPC分类号： H04B1/04
CPC分类号： H04L25/028 , H04L25/0272 , H04L25/0292
摘要： A digital transmission circuit and method providing selectable power consumption via multiple weighted driver slices improves the flexibility of an interface while reducing power consumption when possible. A cascaded series of driver stages is provided by a set of parallel slices and a control logic that activates one or more of the slices, which combine to produce a cascaded active driver circuit. The power consumption/drive level selectability of the slice combination provides a driver that can be fine-tuned to particular applications to provide the required performance at a minimum power consumption level.
摘要翻译： 通过多个加权驱动器片提供可选择的功耗的数字传输电路和方法提高了接口的灵活性，同时在可能的同时降低功耗。 级联的一系列驱动器级由一组并行片提供，并且控制逻辑激活一个或多个片，其组合以产生级联的有源驱动器电路。 切片组合的功耗/驱动器级别可选性提供了可以针对特定应用进行微调的驱动器，以在最小功耗级别提供所需的性能。
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4.发明授权Digital transmission circuit and method providing selectable power consumption via multiple weighted drive slices 有权数字传输电路和方法通过多个加权驱动片提供可选择的功耗公开(公告)号：US07353007B2
公开(公告)日：2008-04-01
申请号：US11050019
申请日：2005-02-03
IPC分类号： H04B1/04
CPC分类号： H04L25/028 , H04L25/0272 , H04L25/0292
摘要： A digital transmission circuit and method providing selectable power consumption via multiple weighted driver slices improves the flexibility of an interface while reducing transmitter power consumption, area and complexity when possible. A cascaded series of driver stages is provided by a set of parallel slices and a control logic that activates one or more of the slices, which combine to produce a cascaded active driver circuit. The power consumption/drive level selectability of the slice combination provides a driver that can be fine-tuned to particular applications to provide the required performance at a minimum power consumption level.
摘要翻译： 通过多个加权驱动器片提供可选择的功耗的数字传输电路和方法提高了接口的灵活性，同时在可能的同时降低了发射机功耗，面积和复杂度。 级联的一系列驱动器级由一组并行片提供，并且控制逻辑激活一个或多个片，其组合以产生级联的有源驱动器电路。 切片组合的功耗/驱动器级别可选性提供了可以针对特定应用进行微调的驱动器，以在最小功耗级别提供所需的性能。
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5.发明授权Digital transmission circuit and interface providing selectable power consumption via multiple weighted driver slices 有权数字传输电路和接口通过多个加权驱动器片提供可选择的功耗公开(公告)号：US08010066B2
公开(公告)日：2011-08-30
申请号：US12024448
申请日：2008-02-01
IPC分类号： H04B1/04
CPC分类号： H04L25/028 , H04L25/0272 , H04L25/0292
摘要： A digital transmission circuit and interface provide selectable power consumption via multiple weighted driver slices, improving the flexibility of an interface while reducing transmitter power consumption, area and complexity when possible. A cascaded series of driver stages is provided by a set of parallel slices and a control logic that activates one or more of the slices, which combine to produce a cascaded active driver circuit. The power consumption/drive level selectability of the slice combination provides a driver that can be fine-tuned to particular applications to provide the required performance at a minimum power consumption level.
摘要翻译： 数字传输电路和接口通过多个加权驱动器片提供可选择的功耗，提高接口的灵活性，同时在可能的同时降低发射机功耗，面积和复杂性。 级联的一系列驱动器级由一组并行片提供，并且控制逻辑激活一个或多个片，其组合以产生级联的有源驱动器电路。 切片组合的功耗/驱动器级别可选性提供了可以针对特定应用进行微调的驱动器，以在最小功耗级别提供所需的性能。
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6.发明授权公开(公告)号：US07522670B2
公开(公告)日：2009-04-21
申请号：US11050605
申请日：2005-02-03
IPC分类号： H04B3/00
CPC分类号： H04L25/028 , H04L25/0272 , H04L25/0292
摘要： A digital transmission circuit and method providing selectable power consumption via single-ended or differential operation improves the flexibility of an interface while reducing power consumption when possible. A differential path is provided through the transmitter output driver stages and portions are selectively disabled when the transmission circuit is in a lower-power operating mode. A single-ended to differential converter circuit can be used to construct a differential signal for output to the final driver stage. The selection of power mode can be made via feedback from a channel quality measurement unit or may be hardwired or selected under programmatic control. The longer delay or skew of the lower-power single-ended mode is compensated for by the relaxed requirements of the channel when conditions permit the use of the lower-power single-ended mode.
摘要翻译： 通过单端或差分操作提供可选择的功耗的数字传输电路和方法提高了接口的灵活性，同时在可能的同时降低功耗。 通过发射机输出驱动器级提供差分路径，并且当传输电路处于低功率操作模式时，部分被选择性地禁用。 单端到差分转换器电路可用于构建差分信号以输出到最终的驱动级。 可以通过来自信道质量测量单元的反馈来进行功率模式的选择，或者可以在编程控制下进行硬连线或选择。 当条件允许使用低功率单端模式时，较低功率单端模式的较长延迟或偏斜由信道的放宽要求进行补偿。
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7.发明授权公开(公告)号：US07443195B2
公开(公告)日：2008-10-28
申请号：US10773427
申请日：2004-02-09
申请人： Juan-Antonio Carballo , Jeffrey L. Burns , Gary Dale Carpenter , Kevin John Nowka , Ivan Vo , Seung-moon Yoo
发明人： Juan-Antonio Carballo , Jeffrey L. Burns , Gary Dale Carpenter , Kevin John Nowka , Ivan Vo , Seung-moon Yoo
IPC分类号： H03K19/0175 , G05F1/10
CPC分类号： H03K19/0008
摘要： A method of reducing power consumption while maintaining performance characteristics and avoiding costly over-design of a high-speed communication link embedded in an SOC is provided. The method includes synthesizing the communication link at a reduced voltage to determine and isolate circuitry that is supply-voltage-critical from circuitry that is non-supply-voltage-critical. The supply-voltage-critical circuitry contains components that may not operate at the reduced voltage without degrading the performance characteristics of the communication link. A non-reduced voltage is used to drive the supply-voltage-critical circuitry while the reduced voltage is used to drive the non-supply-voltage-critical circuitry. The reduced voltage is generated using a voltage regulator embedded in the communication link.
摘要翻译： 提供一种在保持性能特性的同时降低功耗并避免嵌入在SOC中的高速通信链路的昂贵的过度设计的方法。 该方法包括以降低的电压合成通信链路，以确定和隔离与非电源电压关键的电路相关的电源电压关键的电路。 电源电压关键电路包含不降低电压而不降低通信链路性能特性的组件。 使用非降低电压来驱动电源电压关键电路，同时使用降低的电压来驱动非电源电压关键电路。 使用嵌入在通信链路中的电压调节器来产生降低的电压。
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8.发明申请DIGITAL TRANSMISSION CIRCUIT AND INTERFACE PROVIDING SELECTABLE POWER CONSUMPTION VIA MULTIPLE WEIGHTED DRIVER SLICES 有权数字传输电路和接口，通过多个加权驱动器提供可选择的功耗公开(公告)号：US20080125063A1
公开(公告)日：2008-05-29
申请号：US12024448
申请日：2008-02-01
IPC分类号： H01Q11/12
CPC分类号： H04L25/028 , H04L25/0272 , H04L25/0292
摘要： A digital transmission circuit and interface provide selectable power consumption via multiple weighted driver slices, improving the flexibility of an interface while reducing transmitter power consumption, area and complexity when possible. A cascaded series of driver stages is provided by a set of parallel slices and a control logic that activates one or more of the slices, which combine to produce a cascaded active driver circuit. The power consumption/drive level selectability of the slice combination provides a driver that can be fine-tuned to particular applications to provide the required performance at a minimum power consumption level.
摘要翻译： 数字传输电路和接口通过多个加权驱动器片提供可选择的功耗，提高接口的灵活性，同时在可能的同时降低发射机功耗，面积和复杂性。 级联的一系列驱动器级由一组并行片提供，并且控制逻辑激活一个或多个片，其组合以产生级联的有源驱动器电路。 切片组合的功耗/驱动器级别可选性提供了可以针对特定应用进行微调的驱动器，以在最小功耗级别提供所需的性能。
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9.发明申请DIGITAL TRANSMISSION CIRCUIT AND METHOD PROVIDING SELECTABLE POWER CONSUMPTION VIA MULTIPLE WEIGHTED DRIVER SLICES 有权数字传输电路和通过多重加权驱动器提供可选择的功耗的方法公开(公告)号：US20080125062A1
公开(公告)日：2008-05-29
申请号：US12015458
申请日：2008-01-16
IPC分类号： H01Q11/12
CPC分类号： H04L25/028 , H04L25/0272 , H04L25/0292
摘要： A digital transmission circuit and method providing selectable power consumption via multiple weighted driver slices improves the flexibility of an interface while reducing power consumption when possible. A cascaded series of driver stages is provided by a set of parallel slices and a control logic that activates one or more of the slices, which combine to produce a cascaded active driver circuit. The power consumption/drive level selectability of the slice combination provides a driver that can be fine-tuned to particular applications to provide the required performance at a minimum power consumption level.
摘要翻译： 通过多个加权驱动器片提供可选择的功耗的数字传输电路和方法提高了接口的灵活性，同时在可能的同时降低功耗。 级联的一系列驱动器级由一组并行片提供，并且控制逻辑激活一个或多个片，其组合以产生级联的有源驱动器电路。 切片组合的功耗/驱动器级别可选性提供了可以针对特定应用进行微调的驱动器，以在最小功耗级别提供所需的性能。
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10.发明申请Digital transmission circuit and method providing selectable power consumption via multiple weighted driver slices 有权数字传输电路和方法通过多个加权驱动器片提供可选择的功耗公开(公告)号：US20060172715A1
公开(公告)日：2006-08-03
申请号：US11050019
申请日：2005-02-03
申请人： Juan-Antonio Carballo , Kevin Nowka , Ivan Vo , Seung-moon Yoo
发明人： Juan-Antonio Carballo , Kevin Nowka , Ivan Vo , Seung-moon Yoo
CPC分类号： H04L25/028 , H04L25/0272 , H04L25/0292
摘要： A digital transmission circuit and method providing selectable power consumption via multiple weighted driver slices improves the flexibility of an interface while reducing transmitter power consumption, area and complexity when possible. A cascaded series of driver stages is provided by a set of parallel slices and a control logic that activates one or more of the slices, which combine to produce a cascaded active driver circuit. The power consumption/drive level selectability of the slice combination provides a driver that can be fine-tuned to particular applications to provide the required performance at a minimum power consumption level.
摘要翻译： 通过多个加权驱动器片提供可选择的功耗的数字传输电路和方法提高了接口的灵活性，同时在可能的同时降低了发射机功耗，面积和复杂度。 级联的一系列驱动器级由一组并行片提供，并且控制逻辑激活一个或多个片，其组合以产生级联的有源驱动器电路。 切片组合的功耗/驱动器级别可选性提供了可以针对特定应用进行微调的驱动器，以在最小功耗级别提供所需的性能。
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