公开(公告)号：US08728909B2

公开(公告)日：2014-05-20

申请号：US13210654

申请日：2011-08-16

Applicant: Kyung Do Kim

Inventor： Kyung Do Kim

IPC: H01L21/76

CPC classification number: H01L21/76237

Abstract: A semiconductor cell includes first trenches defining fin type active regions within the semiconductor substrate and adjacent to each other, second trenches disposed at one side and the other side of the first trenches, adjacent to the first trench and including fin type active regions, a first oxide layer formed on each of surfaces of the first trenches, and a second oxide layer formed on each of surfaces of the second trenches and having a thicker thickness than the first oxide layer. Although the critical dimension of the fin is increased, the gate drivability can be improved.

Abstract translation: 半导体单元包括在半导体衬底内限定翅片型有源区并且彼此相邻的第一沟槽，设置在与第一沟槽相邻并包括鳍型有源区的第一沟槽的一侧和另一侧的第二沟槽， 形成在第一沟槽的每个表面上的氧化物层，以及形成在第二沟槽的每个表面上并且具有比第一氧化物层更厚的厚度的第二氧化物层。 虽然翅片的临界尺寸增加，但可提高闸门的驾驶性能。

公开(公告)号：US08610203B2

公开(公告)日：2013-12-17

申请号：US13572136

申请日：2012-08-10

Applicant: Kyung Do Kim

Inventor： Kyung Do Kim

IPC: H01L29/66

CPC classification number: H01L27/10876 ,  H01L21/823437 ,  H01L21/823487 ,  H01L27/10891 ,  H01L29/4236

Abstract: A method for manufacturing a semiconductor device comprises forming a buried gate after forming an active region to have a line type. The buried gate comprises an operation gate and a non-operation gate. A height of a gate electrode layer (conductive material) of the non-operation gate is formed to be lower than that of a gate electrode layer of the operation gate, thereby increasing a threshold voltage and preventing an overlap of the ion-implanted active region with the non-operation gate. As a result, a Gate Induced Drain Leakage (GIDL) is prevented to improve a refresh characteristic of the semiconductor device.

Abstract translation: 一种制造半导体器件的方法包括：在形成有源区域之后形成具有线型的掩埋栅极。 掩埋门包括操作门和非操作门。 非操作栅极的栅电极层（导电材料）的高度形成为低于操作栅极的栅极电极层的高度，由此增加阈值电压并防止离子注入的有源区域的重叠 与非操作门。 结果，防止栅极引入漏极泄漏（GIDL）来提高半导体器件的刷新特性。

公开(公告)号：US08263460B2

公开(公告)日：2012-09-11

申请号：US12846577

申请日：2010-07-29

Applicant: Kyung Do Kim

Inventor： Kyung Do Kim

IPC: H01L21/336

CPC classification number: H01L27/10876 ,  H01L21/823437 ,  H01L21/823487 ,  H01L27/10891 ,  H01L29/4236

Abstract: A method for manufacturing a semiconductor device comprises forming a buried gate after forming an active region to have a line type. The buried gate comprises an operational gate and a dummy gate. A height of a gate electrode layer (conductive material) of the dummy gate is formed to be lower than that of a gate electrode layer of the operational gate, thereby increasing a threshold voltage and preventing an overlap of the ion-implanted active region with the dummy gate. As a result, a Gate Induced Drain Leakage (GIDL) is prevented to improve a refresh characteristic of the semiconductor device.

Abstract translation: 一种制造半导体器件的方法包括：在形成有源区域之后形成具有线型的掩埋栅极。 掩埋栅极包括一个操作栅极和一个虚拟栅极。 形成虚拟栅极的栅电极层（导电材料）的高度比操作栅极的栅电极层的高度高，从而增加阈值电压并防止离子注入的有源区与 虚拟门。 结果，防止栅极引入漏极泄漏（GIDL）来提高半导体器件的刷新特性。

公开(公告)号：US07871887B2

公开(公告)日：2011-01-18

申请号：US12137865

申请日：2008-06-12

Applicant: Kyung Do Kim ,  Seung Joo Baek

Inventor： Kyung Do Kim ,  Seung Joo Baek

IPC: H01L21/336 ,  H01L29/76

CPC classification number: H01L29/7827 ,  H01L27/10876 ,  H01L27/10885 ,  H01L29/66666

Abstract: A semiconductor device comprises buried bit lines which are formed to be brought into contact with drain areas of vertical pillar transistors. The buried bit lines are arranged along a first direction in a silicon substrate. The buried bit lines are formed of epi-silicon to reduce the resistance of the buried bit lines.

Abstract translation: 半导体器件包括形成为与垂直柱形晶体管的漏极区域接触的掩埋位线。 埋入的位线沿着硅衬底中的第一方向布置。 掩埋位线由外延硅形成，以减小埋入位线的电阻。

公开(公告)号：US08642428B2

公开(公告)日：2014-02-04

申请号：US12983119

申请日：2010-12-31

Applicant: Kyung Do Kim

Inventor： Kyung Do Kim

IPC: H01L21/336

CPC classification number: H01L29/42328 ,  H01L27/10876

Abstract: A semiconductor device having a line-type active region and a method for manufacturing the same are disclosed. The semiconductor device includes an active region configured in a successive line type, at least one active gate having a first width and crossing the active region, and an isolation gate having a second width different from the first width and being formed between the active gates. The isolation gate's width and the active gate's width are different from each other to guarantee a large storage node contact region, resulting in increased device operation characteristics (write characteristics).

Abstract translation: 公开了一种具有线型有源区的半导体器件及其制造方法。 半导体器件包括配置成连续线类型的有源区，具有第一宽度并与有源区交叉的至少一个有源栅极，以及具有不同于第一宽度的第二宽度并形成在有源栅极之间的隔离栅极。 隔离栅极的宽度和有源栅极宽度彼此不同，以保证大的存储节点接触区域，从而增加器件工作特性（写入特性）。

公开(公告)号：US08143127B2

公开(公告)日：2012-03-27

申请号：US12887694

申请日：2010-09-22

Applicant: Kyung Do Kim

Inventor： Kyung Do Kim

IPC: H01L21/336

CPC classification number: H01L29/66621 ,  H01L21/26506 ,  H01L21/26586 ,  H01L21/3083 ,  H01L29/4236 ,  H01L29/4933 ,  H01L29/6656

Abstract: A semiconductor device includes a silicon substrate; a device isolation structure formed in the silicon substrate to delimit an active region which has a pair of gate forming areas, a drain forming area between the gate forming areas, and source forming areas outside the gate forming areas; an asymmetric bulb-type recess gate formed in each gate forming area of the active region and having the shape of a bulb on the lower end portion of the sidewall thereof facing the source forming area; and source and drain areas respectively formed on the surface of the substrate on both sides of the asymmetric bulb-type recess gate.

Abstract translation: 半导体器件包括硅衬底; 形成在硅衬底中以限制具有一对栅极形成区域的有源区域，栅极形成区域之间的漏极形成区域和栅极形成区域外的源极形成区域的器件隔离结构; 在所述有源区的每个栅极形成区域中形成的非对称的灯泡型凹槽，并且在其侧壁的下端部分上具有与所述源极形成区域相对应的灯泡形状; 以及分别形成在非对称灯泡型凹槽的两侧的基板表面上的源极和漏极区域。

公开(公告)号：US20110248339A1

公开(公告)日：2011-10-13

申请号：US12846577

申请日：2010-07-29

Applicant: Kyung Do Kim

Inventor： Kyung Do Kim

IPC: H01L29/78 ,  H01L21/762 ,  H01L21/336

CPC classification number: H01L27/10876 ,  H01L21/823437 ,  H01L21/823487 ,  H01L27/10891 ,  H01L29/4236

Abstract: A method for manufacturing a semiconductor device comprises forming a buried gate after forming an active region to have a line type. The buried gate comprises an operation gate and a non-operation gate. A height of a gate electrode layer (conductive material) of the non-operation gate is formed to be lower than that of a gate electrode layer of the operation gate, thereby increasing a threshold voltage and preventing an overlap of the ion-implanted active region with the non-operation gate. As a result, a Gate Induced Drain Leakage (GIDL) is prevented to improve a refresh characteristic of the semiconductor device.

Abstract translation: 一种制造半导体器件的方法包括：在形成有源区域之后形成具有线型的掩埋栅极。 掩埋门包括操作门和非操作门。 非操作栅极的栅电极层（导电材料）的高度形成为低于操作栅极的栅极电极层的高度，由此增加阈值电压并防止离子注入的有源区域的重叠 与非操作门。 结果，防止栅极引入漏极泄漏（GIDL）来提高半导体器件的刷新特性。

公开(公告)号：US07999313B2

公开(公告)日：2011-08-16

申请号：US12173949

申请日：2008-07-16

Applicant: Kyung Do Kim

Inventor： Kyung Do Kim

IPC: H01L29/66

CPC classification number: H01L21/823487 ,  H01L27/108 ,  H01L27/10802 ,  H01L29/66666 ,  H01L29/7827 ,  H01L29/7841

Abstract: A semiconductor device includes vertical pillar transistors formed in respective silicon pillars of a silicon substrate. The gates of the vertical pillar transistor are selectively formed on a single surface of lower portions of the silicon pillars, and drain areas of the vertical pillar transistors are connected with one another.

Abstract translation: 半导体器件包括形成在硅衬底的各个硅柱中的垂直柱状晶体管。 垂直柱晶体管的栅极选择性地形成在硅柱的下部的单个表面上，垂直柱状晶体管的漏极区彼此连接。

公开(公告)号：US07655520B2

公开(公告)日：2010-02-02

申请号：US11852415

申请日：2007-09-10

Applicant: Kyung Do Kim

Inventor： Kyung Do Kim

IPC: H01L21/336

CPC classification number: H01L21/28273 ,  H01L21/28291 ,  H01L29/78391 ,  H01L29/7887

Abstract: Disclosed is a non-volatile memory having three data states and a method for manufacturing the same. The non-volatile memory includes a silicon substrate having a device separation film; a floating gate formed on the silicon substrate; a tunnel oxide film interposed between the silicon substrate and the floating gate below both ends of the floating gate; a ferroelectric substance interposed between the silicon substrate and the floating gate inside the tunnel oxide film; a diffusion barrier film enclosing the ferroelectric substance; a control gate formed on the substrate including the floating gate; a gate oxide film formed below the control gate; spacers formed on both lateral walls of the laminated floating gate and control gate including the tunnel oxide film and gate oxide film, respectively; and source/drain regions formed within the substrate surfaces on both sides of the control gate including the spacers, respectively.

Abstract translation: 公开了具有三种数据状态的非易失性存储器及其制造方法。 非易失性存储器包括具有器件分离膜的硅衬底; 形成在硅衬底上的浮置栅极; 隧道氧化膜插入在所述浮动栅极的两端的所述硅衬底和所述浮动栅极之间; 介于硅衬底和隧道氧化膜内部的浮动栅极之间的铁电体; 包围铁电物质的扩散阻挡膜; 形成在包括所述浮动栅极的所述基板上的控制栅极; 形成在控制栅下方的栅氧化膜; 分别形成在叠层浮栅的两个侧壁上，分别形成隧道氧化膜和栅氧化膜的控制栅; 以及分别在包括间隔件的控制栅极的两侧上的衬底表面内形成的源极/漏极区域。

公开(公告)号：US20080079068A1

公开(公告)日：2008-04-03

申请号：US11647875

申请日：2006-12-29

Applicant: Kyung Do Kim

Inventor： Kyung Do Kim

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/66621 ,  H01L21/26506 ,  H01L21/26586 ,  H01L21/3083 ,  H01L29/4236 ,  H01L29/4933 ,  H01L29/6656

Abstract: A semiconductor device includes a silicon substrate; a device isolation structure formed in the silicon substrate to delimit an active region which has a pair of gate forming areas, a drain forming area between the gate forming areas, and source forming areas outside the gate forming areas; an asymmetric bulb-type recess gate formed in each gate forming area of the active region and having the shape of a bulb on the lower end portion of the sidewall thereof facing the source forming area; and source and drain areas respectively formed on the surface of the substrate on both sides of the asymmetric bulb-type recess gate.

Abstract translation: 半导体器件包括硅衬底; 形成在硅衬底中以限制具有一对栅极形成区域的有源区域，栅极形成区域之间的漏极形成区域和栅极形成区域外的源极形成区域的器件隔离结构; 在所述有源区的每个栅极形成区域中形成的非对称的灯泡型凹槽，并且在其侧壁的下端部分上具有与所述源极形成区域相对应的灯泡形状; 以及分别形成在非对称灯泡型凹槽的两侧的基板表面上的源极和漏极区域。