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    Semiconductor fabrication apparatuses to perform semiconductor etching and deposition processes and methods of forming semiconductor device using the same
    2.
    发明授权
    Semiconductor fabrication apparatuses to perform semiconductor etching and deposition processes and methods of forming semiconductor device using the same 有权
    用于执行半导体蚀刻和沉积工艺的半导体制造装置以及使用其形成半导体器件的方法

    公开(公告)号：US08197637B2

    公开(公告)日：2012-06-12

    申请号：US12033266

    申请日：2008-02-19

    申请人： Kyung-Woo Lee ,  Jin-Sung Kim ,  Joo-Byoung Yoon ,  Yeong-Cheol Lee ,  Sang-Jun Park ,  Hee-Kyeong Jeon

    发明人： Kyung-Woo Lee ,  Jin-Sung Kim ,  Joo-Byoung Yoon ,  Yeong-Cheol Lee ,  Sang-Jun Park ,  Hee-Kyeong Jeon

    IPC分类号： H01L21/33

    CPC分类号： H01L21/02087 ,  H01J37/32009 ,  H01J37/32587 ,  H01L21/02057 ,  H01L21/0209

    摘要： A semiconductor fabrication apparatus and a method of fabricating a semiconductor device using the same performs semiconductor etching and deposition processes at an edge of a semiconductor substrate after disposing the semiconductor substrate at a predetermined place in the semiconductor fabrication apparatus. The semiconductor fabrication apparatus has lower, middle and upper electrodes sequentially stacked. The semiconductor substrate is disposed on the middle electrode. Semiconductor etching and deposition processes are performed on the semiconductor substrate in the semiconductor fabrication apparatus. The semiconductor fabrication apparatus forms electrical fields along an edge of the middle electrode during performance of the semiconductor etching and deposition processes.

    摘要翻译： 半导体制造装置和使用该半导体制造装置的半导体装置的制造方法在将半导体基板设置在半导体制造装置中的预定位置之后，在半导体基板的边缘进行半导体蚀刻和沉积处理。 半导体制造装置具有顺序堆叠的下部，中间和上部电极。 半导体衬底设置在中间电极上。 在半导体制造装置中的半导体衬底上进行半导体蚀刻和沉积处理。 半导体制造装置在半导体蚀刻和沉积工艺的执行期间沿着中间电极的边缘形成电场。

    Methods of manufacturing a semiconductor device
    5.
    发明授权
    Methods of manufacturing a semiconductor device 有权
    制造半导体器件的方法

    公开(公告)号：US07375003B2

    公开(公告)日：2008-05-20

    申请号：US11240048

    申请日：2005-09-30

    申请人： Joo-Byoung Yoon ,  Jin-Sung Kim ,  Kyung-Woo Lee ,  Yeong-Cheol Lee ,  Sang-Jun Park ,  Hwan-Shik Park

    发明人： Joo-Byoung Yoon ,  Jin-Sung Kim ,  Kyung-Woo Lee ,  Yeong-Cheol Lee ,  Sang-Jun Park ,  Hwan-Shik Park

    IPC分类号： H01L21/20

    CPC分类号： H01L21/76897 ,  H01L27/10852 ,  H01L28/91

    摘要： In a method of manufacturing a semiconductor device including a capacitor, a first mold layer is formed on a semiconductor substrate. The first mold layer is partially etched to form a first mold layer pattern including an opening for a capacitor. A first lower electrode layer is formed on the first mold layer pattern. A second lower electrode layer including a plurality of first pores is formed on the first lower electrode layer and in the opening. Upper portions of the first lower electrode layer and the second lower electrode layer are removed to form a first lower electrode and a second lower electrode in the opening. A dielectric layer and an upper electrode are successively formed on the first lower electrode and the second lower electrode. Therefore, a capacitor having an enhanced capacitance may be obtained.

    摘要翻译： 在制造包括电容器的半导体器件的方法中，在半导体衬底上形成第一模制层。 部分蚀刻第一模具层以形成包括用于电容器的开口的第一模具层图案。 第一下电极层形成在第一模层图案上。 包括多个第一孔的第二下电极层形成在第一下电极层和开口中。 去除第一下电极层和第二下电极层的上部，以在开口中形成第一下电极和第二下电极。 电介质层和上电极依次形成在第一下电极和第二下电极上。 因此，可以获得具有增大的电容的电容器。

    Methods of manufacturing a semiconductor device
    7.
    发明申请
    Methods of manufacturing a semiconductor device 有权
    制造半导体器件的方法

    公开(公告)号：US20060073691A1

    公开(公告)日：2006-04-06

    申请号：US11240048

    申请日：2005-09-30

    申请人： Joo-Byoung Yoon ,  Jin-Sung Kim ,  Kyung-Woo Lee ,  Yeong-Cheol Lee ,  Sang-Jun Park ,  Hwan-Shik Park

    发明人： Joo-Byoung Yoon ,  Jin-Sung Kim ,  Kyung-Woo Lee ,  Yeong-Cheol Lee ,  Sang-Jun Park ,  Hwan-Shik Park

    IPC分类号： H01L21/44

    CPC分类号： H01L21/76897 ,  H01L27/10852 ,  H01L28/91

    摘要： In a method of manufacturing a semiconductor device including a capacitor, a first mold layer is formed on a semiconductor substrate. The first mold layer is partially etched to form a first mold layer pattern including an opening for a capacitor. A first lower electrode layer is formed on the first mold layer pattern. A second lower electrode layer including a plurality of first pores is formed on the first lower electrode layer and in the opening. Upper portions of the first lower electrode layer and the second lower electrode layer are removed to form a first lower electrode and a second lower electrode in the opening. A dielectric layer and an upper electrode are successively formed on the first lower electrode and the second lower electrode. Therefore, a capacitor having an enhanced capacitance may be obtained.

    摘要翻译： 在制造包括电容器的半导体器件的方法中，在半导体衬底上形成第一模制层。 部分蚀刻第一模具层以形成包括用于电容器的开口的第一模具层图案。 第一下电极层形成在第一模层图案上。 包括多个第一孔的第二下电极层形成在第一下电极层和开口中。 去除第一下电极层和第二下电极层的上部，以在开口中形成第一下电极和第二下电极。 电介质层和上电极依次形成在第一下电极和第二下电极上。 因此，可以获得具有增大的电容的电容器。

    Capacitor for semiconductor device and method of forming the same
    8.
    发明授权
    Capacitor for semiconductor device and method of forming the same 有权
    用于半导体器件的电容器及其形成方法

    公开(公告)号：US07358557B2

    公开(公告)日：2008-04-15

    申请号：US11503946

    申请日：2006-08-15

    申请人： Yeong-Cheol Lee

    发明人： Yeong-Cheol Lee

    IPC分类号： H01L27/108 ,  H01L29/76

    CPC分类号： H01L28/91 ,  H01L27/10817 ,  H01L27/10852 ,  H01L28/87

    摘要： A capacitor for a semiconductor device includes a lower electrode, a dielectric layer formed on a lower electrode, and an upper electrode formed on the dielectric layer. The lower electrode includes a first layer having a cylindrical shape and a mesh second layer formed on inner sidewalls and the bottom surface of the first layer. Beneficially, the first layer is connected to a conductive region of a semiconductor substrate by a contact plug. The lower electrode can be formed by injecting a catalyst into an opening in which the cylindrical first layer is to be formed before forming the cylindrical first layer.

    摘要翻译： 用于半导体器件的电容器包括下电极，形成在下电极上的电介质层和形成在电介质层上的上电极。 下电极包括具有圆柱形状的第一层和形成在第一层的内侧壁和底表面上的网状第二层。 有利地，第一层通过接触插塞连接到半导体衬底的导电区域。 下部电极可以通过在形成圆柱形第一层之前将催化剂注入到其中将形成圆柱形第一层的开口中而形成。

    Capacitor for semiconductor device and method of forming the same
    9.
    发明申请
    Capacitor for semiconductor device and method of forming the same 有权
    用于半导体器件的电容器及其形成方法

    公开(公告)号：US20050116278A1

    公开(公告)日：2005-06-02

    申请号：US10997866

    申请日：2004-11-29

    申请人： Yeong-Cheol Lee

    发明人： Yeong-Cheol Lee

    IPC分类号： H01L27/108 ,  H01L21/02 ,  H01L21/8242

    CPC分类号： H01L28/91 ,  H01L27/10817 ,  H01L27/10852 ,  H01L28/87

    摘要： A capacitor for a semiconductor device includes a lower electrode, a dielectric layer formed on a lower electrode, and an upper electrode formed on the dielectric layer. The lower electrode includes a first layer having a cylindrical shape and a mesh second layer formed on inner sidewalls and the bottom surface of the first layer. Beneficially, the first layer is connected to a conductive region of a semiconductor substrate by a contact plug. The lower electrode can be formed by injecting a catalyst into an opening in which the cylindrical first layer is to be formed before forming the cylindrical first layer.

    摘要翻译： 用于半导体器件的电容器包括下电极，形成在下电极上的电介质层和形成在电介质层上的上电极。 下电极包括具有圆柱形状的第一层和形成在第一层的内侧壁和底表面上的网状第二层。 有利地，第一层通过接触插塞连接到半导体衬底的导电区域。 下部电极可以通过在形成圆柱形第一层之前将催化剂注入到其中将形成圆柱形第一层的开口中而形成。

    Capacitor for semiconductor device and method of forming the same
    10.
    发明申请
    Capacitor for semiconductor device and method of forming the same 有权

    公开(公告)号：US20060273369A1

    公开(公告)日：2006-12-07

    申请号：US11503946

    申请日：2006-08-15

    申请人： Yeong-Cheol Lee

    发明人： Yeong-Cheol Lee

    IPC分类号： H01L29/94

    CPC分类号： H01L28/91 ,  H01L27/10817 ,  H01L27/10852 ,  H01L28/87

    摘要： A capacitor for a semiconductor device includes a lower electrode, a dielectric layer formed on a lower electrode, and an upper electrode formed on the dielectric layer. The lower electrode includes a first layer having a cylindrical shape and a mesh second layer formed on inner sidewalls and the bottom surface of the first layer. Beneficially, the first layer is connected to a conductive region of a semiconductor substrate by a contact plug. The lower electrode can be formed by injecting a catalyst into an opening in which the cylindrical first layer is to be formed before forming the cylindrical first layer.