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公开(公告)号：US20150380050A1
公开(公告)日：2015-12-31
申请号：US14318665
申请日：2014-06-29
Applicant: LSI Corporation
Inventor： Victor Krachkovsky , Razmik Karabed , Shaohua Yang , Wu Chang
IPC: G11B20/12
CPC classification number: G11B20/1217 , G11B20/1833 , H03M7/4006 , H03M13/1102
Abstract: A storage system includes a storage medium operable to maintain a data set, a read/write head assembly operable to write the data set to the storage medium and to read the data set from the storage medium, a multi-level enumerative encoder operable to encode the data set before it is written to the storage medium as encoded data, wherein the enumerative encoder applies an enumeration using a plurality of level-dependent bases, and a decoder operable to decode the data set after it is read from the storage medium.
Abstract translation: 存储系统包括可操作以保持数据集的存储介质，可操作以将数据集写入存储介质并从存储介质读取数据集的读/写头组件，可操作以编码的多级枚举编码器 其前的数据集作为编码数据被写入存储介质，其中该枚举编码器使用多个依赖于水平的基站来应用枚举，以及解码器，用于在从存储介质读取数据集之后对其进行解码。
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公开(公告)号：US09003263B2
公开(公告)日：2015-04-07
申请号：US13742340
申请日：2013-01-15
Applicant: LSI Corporation
Inventor： Razmik Karabed , Shaohua Yang , Wu Chang , Victor Krachkovsky
CPC classification number: G06F11/14 , G11B20/1833 , G11C11/26 , G11C11/5628 , G11C11/5642 , H03M5/145
Abstract: A method of generating a hardware encoder includes generating a first directed graph characterizing a constraint set for a constrained system, identifying a scaling factor for an approximate eigenvector for the first directed graph, applying the scaling factor to the approximate eigenvector for the first directed graph to yield a scaled approximate eigenvector, partitioning arcs between each pair of states in the first directed graph, performing a state splitting operation on the first directed graph according to the partitioning of the arcs to yield a second directed graph, and generating the hardware encoder based on the second directed graph.
Abstract translation: 生成硬件编码器的方法包括：生成表征约束系统的约束集的第一有向图，识别第一有向图的近似特征向量的缩放因子，将缩放因子应用于第一有向图的近似特征向量 产生缩放的近似特征向量，在第一有向图中的每对状态之间划分弧，根据弧的划分对第一有向图执行状态分割操作以产生第二有向图，并且基于 第二个有向图。
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公开(公告)号：US08724243B1
公开(公告)日：2014-05-13
申请号：US13707898
申请日：2012-12-07
Applicant: LSI Corporation
Inventor： Razmik Karabed , Shaohua Yang , Wu Chang , Victor A. Krachkovsky
CPC classification number: G11B20/1426 , H03M7/46
Abstract: Systems and methods relating generally to processing information, and more particularly without limitation to systems and methods for encoding data sets.
Abstract translation: 一般涉及处理信息的系统和方法，更具体而言，不限于用于编码数据集的系统和方法。
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公开(公告)号：US20140201585A1
公开(公告)日：2014-07-17
申请号：US13742340
申请日：2013-01-15
Applicant: LSI Corporation
Inventor： Razmik Karabed , Shaohua Yang , Wu Chang , Victor Krachkovsky
IPC: G06F11/14
CPC classification number: G06F11/14 , G11B20/1833 , G11C11/26 , G11C11/5628 , G11C11/5642 , H03M5/145
Abstract: Various embodiments of the present invention provide systems and methods for encoding and decoding data for constrained systems with state-split based encoders and decoders.
Abstract translation: 本发明的各种实施例提供了用于基于状态分割的编码器和解码器的受限制系统的数据的编码和解码的系统和方法。
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5.发明申请公开(公告)号：US20140115381A1
公开(公告)日：2014-04-24
申请号：US13654931
申请日：2012-10-18
Applicant: LSI CORPORATION
Inventor： Wu Chang , Razmik Karabed , Fan Zhang
CPC classification number: G11B20/1833 , G11B20/10277 , G11B20/10287
Abstract: Techniques are described for constructing maximum transition run (MTR) modulation code based upon a multi-level (ML) run-length limited (RLL) finite state machine (FSM) that implements different sets of penalties. A processor is configured to receive information from a hard disk drive (HDD) via a read channel and recover data from the HDD using MTR modulation code. A memory has computer executable instructions configured for execution by the processor to model a magnetic recording channel as a partial response channel, model a source of information to the magnetic recording channel to provide an optimized Markov source, and construct an MTR modulation code to mimic the optimized Markov source based upon an FSM having a limited transition run length and a multi-level periodic structure. The FSM provides at least two different sets of penalties in a period.
Abstract translation: 描述了基于实现不同处罚集的多级（ML）游程限制（RLL）有限状态机（FSM）来构建最大过渡运行（MTR）调制码的技术。 处理器被配置为经由读通道从硬盘驱动器（HDD）接收信息，并且使用MTR调制码从HDD恢复数据。 存储器具有被配置为由处理器执行以将磁记录通道建模为部分响应通道的计算机可执行指令，将信息源建模到磁记录通道以提供优化的马尔可夫源，并构建MTR调制码以模拟 基于具有有限转换行程长度和多级周期结构的FSM的优化马尔可夫源。 FSM在一段时间内至少提供两套不同的罚则。
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Patent Agency Ranking
公开(公告)号：US09251845B2
公开(公告)日：2016-02-02
申请号：US14318665
申请日：2014-06-29
Applicant: LSI Corporation
Inventor： Victor Krachkovsky , Razmik Karabed , Shaohua Yang , Wu Chang
CPC classification number: G11B20/1217 , G11B20/1833 , H03M7/4006 , H03M13/1102
Abstract: A storage system includes a storage medium operable to maintain a data set, a read/write head assembly operable to write the data set to the storage medium and to read the data set from the storage medium, a multi-level enumerative encoder operable to encode the data set before it is written to the storage medium as encoded data, wherein the enumerative encoder applies an enumeration using a plurality of level-dependent bases, and a decoder operable to decode the data set after it is read from the storage medium.
Abstract translation: 存储系统包括可操作以保持数据集的存储介质，可操作以将数据集写入存储介质并从存储介质读取数据集的读/写头组件，可操作以编码的多级枚举编码器 其前的数据集作为编码数据被写入存储介质，其中该枚举编码器使用多个依赖于水平的基站来应用枚举，以及解码器，用于在从存储介质读取数据集之后对其进行解码。
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7.发明授权Multi-level run-length limited finite state machine for magnetic recording channel 有权用于磁记录通道的多级游程限制有限状态机公开(公告)号：US08854755B2
公开(公告)日：2014-10-07
申请号：US13654893
申请日：2012-10-18
Applicant: LSI Corporation
Inventor： Wu Chang , Razmik Karabed , Shaohua Yang , Fan Zhang
CPC classification number: G11B5/02 , G06F11/16 , G11B20/10277
Abstract: A system is described for constructing maximum transition run modulation code based upon a multi-level run-length limited finite state machine. A processor is configured to receive information from a hard disk drive via a read channel and recover data from the hard disk drive using maximum transition run modulation code. A memory has computer executable instructions configured for execution by the processor to model a magnetic recording channel as a partial response channel, model a source of information to the magnetic recording channel to provide an optimized Markov source, and construct a maximum transition run modulation code to mimic the optimized Markov source based upon a finite state machine having a limited transition run length and a multi-level periodic structure.
Abstract translation: 描述了一种基于多级游程限制有限状态机来构建最大过渡运行调制码的系统。 处理器被配置为经由读取通道从硬盘驱动器接收信息，并使用最大过渡运行调制码从硬盘驱动器恢复数据。 存储器具有被配置为由处理器执行以将磁记录通道建模为部分响应通道的计算机可执行指令，将信息源建模到磁记录通道以提供优化马尔可夫源，并且构建最大过渡运行调制码 基于具有有限转换行程长度和多级周期性结构的有限状态机模拟优化的马尔可夫源。
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公开(公告)号：US08792195B2
公开(公告)日：2014-07-29
申请号：US13654931
申请日：2012-10-18
Applicant: LSI Corporation
Inventor： Wu Chang , Razmik Karabed , Fan Zhang
CPC classification number: G11B20/1833 , G11B20/10277 , G11B20/10287
Abstract: Techniques are described for constructing maximum transition run (MTR) modulation code based upon a multi-level (ML) run-length limited (RLL) finite state machine (FSM) that implements different sets of penalties. A processor is configured to receive information from a hard disk drive (HDD) via a read channel and recover data from the HDD using MTR modulation code. A memory has computer executable instructions configured for execution by the processor to model a magnetic recording channel as a partial response channel, model a source of information to the magnetic recording channel to provide an optimized Markov source, and construct an MTR modulation code to mimic the optimized Markov source based upon an FSM having a limited transition run length and a multi-level periodic structure. The FSM provides at least two different sets of penalties in a period.
Abstract translation: 描述了基于实现不同处罚集的多级（ML）游程限制（RLL）有限状态机（FSM）来构建最大过渡运行（MTR）调制码的技术。 处理器被配置为经由读通道从硬盘驱动器（HDD）接收信息，并且使用MTR调制码从HDD恢复数据。 存储器具有被配置为由处理器执行以将磁记录通道建模为部分响应通道的计算机可执行指令，将信息源建模到磁记录通道以提供优化的马尔可夫源，并构建MTR调制码以模拟 基于具有有限转换行程长度和多级周期结构的FSM的优化马尔可夫源。 FSM在一段时间内至少提供两套不同的罚则。
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9.发明申请MULTI-LEVEL RUN-LENGTH LIMITED FINITE STATE MACHINE FOR MAGNETIC RECORDING CHANNEL 有权多级运行有限公司有限公司磁记录通道有限公司公开(公告)号：US20140111880A1
公开(公告)日：2014-04-24
申请号：US13654893
申请日：2012-10-18
Applicant: LSI CORPORATION
Inventor： Wu Chang , Razmik Karabed , Shaohua Yang , Fan Zhang
IPC: G11B5/02
CPC classification number: G11B5/02 , G06F11/16 , G11B20/10277
Abstract: A system is described for constructing maximum transition run modulation code based upon a multi-level run-length limited finite state machine. A processor is configured to receive information from a hard disk drive via a read channel and recover data from the hard disk drive using maximum transition run modulation code. A memory has computer executable instructions configured for execution by the processor to model a magnetic recording channel as a partial response channel, model a source of information to the magnetic recording channel to provide an optimized Markov source, and construct a maximum transition run modulation code to mimic the optimized Markov source based upon a finite state machine having a limited transition run length and a multi-level periodic structure.
Abstract translation: 描述了一种基于多级游程限制有限状态机来构建最大过渡运行调制码的系统。 处理器被配置为经由读取通道从硬盘驱动器接收信息，并使用最大过渡运行调制码从硬盘驱动器恢复数据。 存储器具有被配置为由处理器执行以将磁记录通道建模为部分响应通道的计算机可执行指令，将信息源建模到磁记录通道以提供优化马尔可夫源，并且构建最大过渡运行调制码 基于具有有限转换行程长度和多级周期性结构的有限状态机模拟优化的马尔可夫源。
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公开(公告)号：US20140223136A1
公开(公告)日：2014-08-07
申请号：US13761892
申请日：2013-02-07
Applicant: LSI CORPORATION
Inventor： Zhiwei Wu , Zhi Bin Li , Xiangdong Guo , Rui Shen , Razmik Karabed , Wu Chang
IPC: G06F12/10
CPC classification number: G06F12/1009
Abstract: The disclosure is directed to a system and method for accessing one or more values of a lookup table. In some embodiments, one or more read only memory devices are configured for storing a first plurality of values of the lookup table, and one or more combinational logic circuits are configured for accessing a second plurality of values of the lookup table. At least one of hardware area and timing pressures are mitigated through various storage and access schemes.
Abstract translation: 本公开针对用于访问查找表的一个或多个值的系统和方法。 在一些实施例中，一个或多个只读存储器设备被配置为存储查找表的第一多个值，并且一个或多个组合逻辑电路被配置用于访问查找表的第二多个值。 通过各种存储和访问方案来减轻硬件面积和时序压力中的至少一个。
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