公开(公告)号：US06444919B1

公开(公告)日：2002-09-03

申请号：US08477054

申请日：1995-06-07

申请人： Laertis Economikos ,  Mukta Shaji Farooq ,  Michael Ford McAllister ,  Eric Daniel Perfecto ,  Chandrika Prasad ,  Keshav Prasad ,  Madhavan Swaminathan ,  Thomas Anthony Wassick ,  George White

发明人： Laertis Economikos ,  Mukta Shaji Farooq ,  Michael Ford McAllister ,  Eric Daniel Perfecto ,  Chandrika Prasad ,  Keshav Prasad ,  Madhavan Swaminathan ,  Thomas Anthony Wassick ,  George White

IPC分类号： H05K103

CPC分类号： H01L23/5382 ,  H01L2924/0002 ,  H01L2924/09701 ,  H05K1/0286 ,  H05K1/0289 ,  H05K3/467 ,  H01L2924/00

摘要： A thin film wiring scheme on a substrate. The thin film wiring scheme includes a plurality of chip connection pads at each of a first and second chip site on the substrate, a plurality of directional wiring lines interspersed between the chip connection pads at each of the first and second chip sites, at least one of the directional wiring lines being orthogonal to at least one of the other directional wiring lines at each of the first and second chip sites, and a plurality of chip site interconnection lines connecting directional wiring lines at the first chip site with the directional wiring lines at the second chip site.

摘要翻译： 基板上的薄膜布线方案。 薄膜布线方案包括在基板上的第一和第二芯片位置的每一个处的多个芯片连接焊盘，散布在第一和第二芯片位置中的每一个的芯片连接焊盘之间的多个定向布线，至少一个 所述定向布线与所述第一和第二芯片位置中的每一个处的所述其它方向布线中的至少一个正交;以及多个芯片布线，其将所述第一芯片位置处的方向布线与所述定向布线连接， 第二个芯片站点。

公开(公告)号：US5705857A

公开(公告)日：1998-01-06

申请号：US618023

申请日：1996-03-25

申请人： Mukta Shaji Farooq ,  Suryanarayana Kaja ,  Eric Daniel Perfecto ,  George Eugene White

发明人： Mukta Shaji Farooq ,  Suryanarayana Kaja ,  Eric Daniel Perfecto ,  George Eugene White

IPC分类号： H01L23/498 ,  H01L23/532 ,  H05K1/03 ,  H05K3/06 ,  H05K3/10 ,  H05K3/38 ,  H05K3/46 ,  H01L23/48

CPC分类号： H05K3/108 ,  H01L23/498 ,  H01L23/49866 ,  H01L23/53228 ,  H01L2924/0002 ,  H01L2924/09701 ,  H05K1/0306 ,  H05K2203/0597 ,  H05K2203/1105 ,  H05K3/062 ,  H05K3/388 ,  H05K3/4644

摘要： The present invention relates generally to a new structure and method for capped copper electrical interconnects. More particularly, the invention encompasses a novel structure in which one or more of the copper electrical interconnects within a semiconductor substrate are capped to obtain a robust electrical interconnect structure. A method for obtaining such capped copper electrical interconnect structure is also disclosed. These capped interconnects can be a single layer or multi-layer structures. Similarly, the interconnect structure that is being capped can itself be composed of single or multi-layered material.

公开(公告)号：US5898222A

公开(公告)日：1999-04-27

申请号：US950262

申请日：1997-10-14

申请人： Mukta Shaji Farooq ,  Suryanarayana Kaja ,  Eric Daniel Perfecto ,  George Eugene White

发明人： Mukta Shaji Farooq ,  Suryanarayana Kaja ,  Eric Daniel Perfecto ,  George Eugene White

IPC分类号： H01L23/498 ,  H01L23/532 ,  H05K1/03 ,  H05K3/06 ,  H05K3/10 ,  H05K3/38 ,  H05K3/46 ,  H01L23/48

CPC分类号： H05K3/108 ,  H01L23/498 ,  H01L23/49866 ,  H01L23/53228 ,  H01L2924/0002 ,  H01L2924/09701 ,  H05K1/0306 ,  H05K2203/0597 ,  H05K2203/1105 ,  H05K3/062 ,  H05K3/388 ,  H05K3/4644

摘要： The present invention relates generally to a new structure and method for capped copper electrical interconnects. More particularly, the invention encompasses a novel structure in which one or more of the copper electrical interconnects within a semiconductor substrate are capped to obtain a robust electrical interconnect structure. A method for obtaining such capped copper electrical interconnect structure is also disclosed. These capped interconnects can be a single layer or multi-layer structures. Similarly, the interconnect structure that is being capped can itself be composed of single or multi-layered material.

摘要翻译： 本发明一般涉及一种用于封盖铜电互连的新结构和方法。 更具体地，本发明包括一种新颖的结构，其中半导体衬底内的一个或多个铜电互连被封盖以获得坚固的电互连结构。 还公开了一种用于获得这种封盖铜电互连结构的方法。 这些封装的互连可以是单层或多层结构。 类似地，被封装的互连结构本身可以由单层或多层材料组成。

公开(公告)号：US5874369A

公开(公告)日：1999-02-23

申请号：US761028

申请日：1996-12-05

申请人： Mukta Shaji Farooq ,  Mark Joseph LaPlante

发明人： Mukta Shaji Farooq ,  Mark Joseph LaPlante

IPC分类号： H01L21/02 ,  H01L21/768 ,  C03C25/06

CPC分类号： H01L21/76802 ,  H01L28/55

摘要： Vias are formed in a dielectric film overlying an electrode layer by sweeping a laser beam over the area in which the via is to be formed. In particular, a Nd:YAG laser, producing a beam of light having a 266 nm wave length, effectively ablates a barium strontium titanate dielectric film, without adversely affecting an underlying platinum electrode. The present invention overcomes the problem of wet chemical etching of dielectric films to form vias. Wet chemical etching often requires etchants that adversely affect the underlying metal electrode and typically require the use of environmentally undesirable chemicals.

摘要翻译： 通过在要形成通孔的区域上扫掠激光束，在覆盖电极层的电介质膜中形成通孔。 特别地，产生具有266nm波长的光束的Nd：YAG激光器有效地烧蚀钛酸锶钡电介质膜，而不会对下面的铂电极产生不利影响。 本发明克服了介电膜的湿化学蚀刻形成通孔的问题。 湿式化学蚀刻通常需要对底层金属电极产生不利影响的蚀刻剂，通常需要使用对环境无害的化学品。

公开(公告)号：US5912044A

公开(公告)日：1999-06-15

申请号：US782205

申请日：1997-01-10

申请人： Mukta Shaji Farooq ,  Ajay P. Giri ,  Rajesh Shankerial Patel

发明人： Mukta Shaji Farooq ,  Ajay P. Giri ,  Rajesh Shankerial Patel

IPC分类号： H01L21/02 ,  H05K1/03 ,  H05K1/16 ,  H05K3/00 ,  H05K3/46 ,  B05D5/12

CPC分类号： H01L28/40 ,  H01L28/55 ,  H05K1/162 ,  H05K1/0306 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K3/0029 ,  H05K3/4605 ,  Y10T29/435

摘要： Thin film capacitors are formed by a multi-level dry processing method that includes simultaneous ablation of via openings through both the dielectric and the metal electrode layers of a capacitor. Preferably, the dielectric films are formed of barium strontium titanate and the metal electrode layers are formed of platinum. The present invention overcomes the problems associated with the use of strong etchants to sequentially form separate via openings through the electrode and dielectric layers, prevents the potential for delamination of the respective layers during wet etching and the possible undesirable effects of etching solutions on substrate materials.

摘要翻译： 薄膜电容器通过多级干法处理方法形成，其包括通过电容器的电介质和金属电极层的同时烧蚀通孔。 优选地，电介质膜由钛酸钡锶形成，并且金属电极层由铂形成。 本发明克服了与使用强蚀刻剂顺序地通过电极和电介质层形成单独的通路孔相关的问题，防止在湿蚀刻期间各层分层的可能性以及蚀刻溶液对衬底材料的可能不期望的影响。

公开(公告)号：US06226863B1

公开(公告)日：2001-05-08

申请号：US09366980

申请日：1999-08-04

申请人： Mukta Shaji Farooq ,  Raymond Alan Jackson ,  Sudipta Kumar Ray

发明人： Mukta Shaji Farooq ,  Raymond Alan Jackson ,  Sudipta Kumar Ray

IPC分类号： H05K334

CPC分类号： G01R1/0408 ,  H01L23/49816 ,  H01L23/642 ,  H01L24/48 ,  H01L24/49 ,  H01L24/75 ,  H01L24/85 ,  H01L2224/16 ,  H01L2224/16145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2224/75 ,  H01L2224/85 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/1532 ,  H01L2924/15787 ,  H01L2924/16195 ,  H01L2924/19041 ,  H01L2924/19104 ,  H01L2924/30105 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49146 ,  H01L2224/78 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/0401

摘要： A device and method for enabling the reworkability of an integrated circuit comprising a wirebond chip having a bottom surface and a carrier substrate having a first surface and a second surface. The first surface and second surface of the carrier substrate are electrically connected through a series of vias. A bonding agent is used to mechanically attach the wirebond chip to the carrier substrate in addition to wirebonds for electrically connecting the wirebond chip to the substrate. The substrate is attached to a multi-chip module (MCM) by ball grid array (BGA) or controlled collapse chip connection (C4) attaching process.

摘要翻译： 一种能够实现包括具有底表面的引线键合芯片和具有第一表面和第二表面的载体基板的集成电路的可再加工性的装置和方法。 载体基板的第一表面和第二表面通过一系列通孔电连接。 除了用于将引线芯片电连接到基板的引线之外，还使用粘合剂将引线键合芯片机械地附接到载体基板。 基板通过球栅阵列（BGA）或受控的崩溃芯片连接（C4）连接工艺连接到多芯片模块（MCM）。

公开(公告)号：US6015955A

公开(公告)日：2000-01-18

申请号：US879718

申请日：1997-06-20

申请人： Mukta Shaji Farooq ,  Raymond Alan Jackson ,  Sudipta Kumar Ray

发明人： Mukta Shaji Farooq ,  Raymond Alan Jackson ,  Sudipta Kumar Ray

IPC分类号： G01R1/04 ,  H01L21/60 ,  H01L23/498 ,  H01L23/64 ,  H05K7/02

CPC分类号： G01R1/0408 ,  H01L23/49816 ,  H01L23/642 ,  H01L24/75 ,  H01L24/85 ,  H01L2224/16 ,  H01L2224/16145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2224/75 ,  H01L2224/85 ,  H01L2224/92247 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/1532 ,  H01L2924/15787 ,  H01L2924/16195 ,  H01L2924/19041 ,  H01L2924/19104 ,  H01L2924/30105 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49146

摘要： A device and method for enabling the reworkability of an integrated circuit. The device includes a wirebond chip having a bottom surface and a carrier substrate having a first surface and a second surface. The first surface and second surface of the carrier substrate are electrically connected through a series of vias. A bonding agent is used to mechanically attach the wirebond chip to the carrier substrate in addition to wirebonds for electrically connecting the wirebond chip to the substrate. The substrate is attached to a multi-chip module (MCM) by ball grid array (BGA) or controlled collapse chip connection (C4) attaching process.

摘要翻译： 一种用于实现集成电路的可再加工性的装置和方法。 该器件包括具有底表面的引线键合芯片和具有第一表面和第二表面的载体衬底。 载体基板的第一表面和第二表面通过一系列通孔电连接。 除了用于将引线芯片电连接到基板的引线之外，还使用粘合剂将引线键合芯片机械地附接到载体基板。 基板通过球栅阵列（BGA）或受控的崩溃芯片连接（C4）连接工艺连接到多芯片模块（MCM）。