公开(公告)号：US20190148190A1

公开(公告)日：2019-05-16

申请号：US16247509

申请日：2019-01-14

申请人： Lam Research Corporation

发明人： Eric Pape ,  Darrell Ehrlich ,  Mike Jing

IPC分类号： H01L21/67 ,  G01K1/14 ,  G01K1/02 ,  H01L21/683 ,  G01K7/00 ,  H01L21/673

摘要： A substrate holder includes a base plate, a bond layer disposed over the base plate, and a ceramic layer disposed over the bond layer. The ceramic layer has a top surface including an area configured to support a substrate. A number of temperature measurement electrical devices are attached to the ceramic layer. Electrically conductive traces are embedded within the ceramic layer and positioned and routed to electrically connect with one or more of electrical contacts of the number of temperature measurement electrical devices. Electrical wires are disposed to electrically contact the electrically conductive traces. The electrical wires extend from the ceramic layer through the bond layer and through the base plate to a control circuit.

公开(公告)号：US20150053347A1

公开(公告)日：2015-02-26

申请号：US14470544

申请日：2014-08-27

申请人： Lam Research Corporation

发明人： Yoshie Kimura ,  Tom Kamp ,  Eric Pape ,  Rohit DeshPande ,  Keith Gaff ,  Gowri Kamarthy

IPC分类号： H01L21/66 ,  H01L21/67

CPC分类号： H01L22/26 ,  H01J37/32724 ,  H01J37/32926 ,  H01J37/32935 ,  H01L21/67069 ,  H01L21/67248 ,  H01L22/12 ,  H01L22/20 ,  H01L2924/0002 ,  H01L2924/00

摘要： Exemplary embodiments are directed to controlling CD uniformity of a wafer by controlling trim time on temperature in a plasma processing system. The plasma processing system has a wafer support assembly including a plurality of independently controllable temperature control zones across a chuck and a controller that controls each temperature control zone. The controller receives process control and temperature data associated with at least one wafer previously processed in a plasma chamber of the plasma processing system. The controller also receives critical device parameters of a current wafer to be processed in the plasma chamber. The controller calculates a target trim time and a target temperature profile of the current wafer based on the process control and temperature data of the at least one previously processed wafers and the critical device parameters of the current wafer. The current wafer as subjected to a trimming operation for a duration of the target trim time while controlling temperatures in the temperature control zones to thereby control temperature of each device die location based on the target temperature profile.

摘要翻译： 示例性实施例涉及通过控制等离子体处理系统中的温度调节时间来控制晶片的CD均匀性。 等离子体处理系统具有晶片支撑组件，其包括横跨卡盘的多个可独立控制的温度控制区域和控制每个温度控制区域的控制器。 控制器接收与先前在等离子体处理系统的等离子体室中处理的至少一个晶片相关联的过程控制和温度数据。 控制器还接收等离子体室中要处理的当前晶片的关键器件参数。 控制器基于至少一个先前处理的晶片的过程控制和温度数据以及当前晶片的关键器件参数来计算当前晶片的目标修整时间和目标温度分布。 当前的晶片在控制温度控制区域中的温度的同时进行修整操作，同时控制温度控制区域中的温度，从而基于目标温度分布来控制每个器件管芯位置的温度。

公开(公告)号：US20140220709A1

公开(公告)日：2014-08-07

申请号：US13758266

申请日：2013-02-04

申请人： LAM RESEARCH CORPORATION

发明人： Yoshie Kimura ,  Tom Kamp ,  Eric Pape ,  Rohit DeshPande ,  Keith Gaff ,  Gowri Kamarthy

IPC分类号： H01L21/66 ,  H01L21/67

CPC分类号： H01L22/26 ,  H01J37/32724 ,  H01J37/32926 ,  H01J37/32935 ,  H01L21/67069 ,  H01L21/67248 ,  H01L22/12 ,  H01L22/20 ,  H01L2924/0002 ,  H01L2924/00

摘要： Exemplary embodiments are directed to controlling CD uniformity of a wafer by controlling trim time on temperature in a plasma processing system. The plasma processing system has a wafer support assembly including a plurality of independently controllable temperature control zones across a chuck and a controller that controls each temperature control zone. The controller receives process control and temperature data associated with at least one wafer previously processed in a plasma chamber of the plasma processing system, and critical device parameters of a current wafer to be processed in the plasma chamber. The controller calculates a target trim time and a target temperature profile of the current wafer based on the process control and temperature data, and the critical device parameters. The current wafer is trimmed during the target trim time while the temperature of each device die location is controlled based on the target temperature profile.

摘要翻译： 示例性实施例涉及通过控制等离子体处理系统中的温度调节时间来控制晶片的CD均匀性。 等离子体处理系统具有晶片支撑组件，其包括横跨卡盘的多个可独立控制的温度控制区域和控制每个温度控制区域的控制器。 控制器接收与先前在等离子体处理系统的等离子体室中处理的至少一个晶片相关联的过程控制和温度数据，以及在等离子体室中待处理的当前晶片的关键器件参数。 控制器基于过程控制和温度数据以及关键设备参数来计算当前晶片的目标修整时间和目标温度分布。 在目标修整时间期间修剪当前晶片，同时基于目标温度分布来控制每个器件管芯位置的温度。

公开(公告)号：US20190166700A1

公开(公告)日：2019-05-30

申请号：US15825682

申请日：2017-11-29

申请人： Lam Research Corporation

发明人： Eric Pape ,  Changyou Jing ,  Fred Dennis Egley

IPC分类号： H05K3/46 ,  H01L21/683 ,  H05K3/24 ,  H05K3/42 ,  H05K3/00 ,  H05K1/02

摘要： A substrate processing system includes a processing chamber, a pedestal arranged in the processing chamber, and an electrostatic chuck (ESC) arranged on the pedestal. The ESC contains a printed circuit board assembly (PCBA) made up of a plurality of printed circuit board layers to mount circuitry that controls operation of the ESC. One or more of the printed circuit board layers includes a heater layer having one or more metal traces, which may be copper, to cover some or all of a surface of the heater layer sufficiently to provide heat to one or more of the remaining printed circuit board layers, to maintain the circuitry within a predetermined temperature range. The heat may be conducted directly among the various other printed circuit board layers, or may be conducted through vias in various ones of the printed circuit board layers.

公开(公告)号：US10306776B1

公开(公告)日：2019-05-28

申请号：US15825682

申请日：2017-11-29

申请人： Lam Research Corporation

发明人： Eric Pape ,  Changyou Jing ,  Fred Dennis Egley

IPC分类号： H05K1/02 ,  H05K3/46 ,  H01L21/683 ,  H05K3/24 ,  H05K3/00 ,  H05K3/42

摘要： A substrate processing system includes a processing chamber, a pedestal arranged in the processing chamber, and an electrostatic chuck (ESC) arranged on the pedestal. The ESC contains a printed circuit board assembly (PCBA) made up of a plurality of printed circuit board layers to mount circuitry that controls operation of the ESC. One or more of the printed circuit board layers includes a heater layer having one or more metal traces, which may be copper, to cover some or all of a surface of the heater layer sufficiently to provide heat to one or more of the remaining printed circuit board layers, to maintain the circuitry within a predetermined temperature range. The heat may be conducted directly among the various other printed circuit board layers, or may be conducted through vias in various ones of the printed circuit board layers.

公开(公告)号：US20140065835A1

公开(公告)日：2014-03-06

申请号：US13954416

申请日：2013-07-30

申请人： Lam Research Corporation

发明人： Bobby Kadkhodayan ,  Jon McChesney ,  Eric Pape ,  Rajinder Dhindsa

IPC分类号： H01L21/3065 ,  H01L21/02 ,  H01L21/67

CPC分类号： H01L21/3065 ,  C23C14/564 ,  C23C16/4401 ,  C23C16/505 ,  H01J37/16 ,  H01J37/32091 ,  H01J37/32495 ,  H01J37/32568 ,  H01J2237/0213 ,  H01L21/02104 ,  H01L21/67017 ,  H01L21/67069

摘要： A flexible polymer or elastomer coated RF return strap to be used in a plasma chamber to protect the RF strap from plasma generated radicals such as fluorine and oxygen radicals, and a method of processing a semiconductor substrate with reduced particle contamination in a plasma processing apparatus. The coated RF strap minimizes particle generation and exhibits lower erosion rates than an uncoated base component. Such a coated member having a flexible coating on a conductive flexible base component provides an RF ground return configured to allow movement of one or more electrodes in an adjustable gap capacitively coupled plasma reactor chamber.

摘要翻译： 用于等离子体室中的柔性聚合物或弹性体涂覆的RF返回带，以保护RF带免受等离子体产生的自由基，例如氟和氧自由基，以及在等离子体处理装置中处理具有减少的颗粒污染的半导体衬底的方法。 涂覆的RF带最小化颗粒产生并且比未涂覆的基底部件具有更低的侵蚀速率。 这种在导电柔性基座部件上具有柔性涂层的涂覆部件提供了RF接地回路，其被配置为允许一个或多个电极在可调节间隙电容耦合等离子体反应器室中移动。

公开(公告)号：US20170098564A1

公开(公告)日：2017-04-06

申请号：US14874991

申请日：2015-10-05

申请人： Lam Research Corporation

发明人： Eric Pape ,  Darrell Ehrlich ,  Mike Jing

IPC分类号： H01L21/67 ,  G01K7/00 ,  H01L21/673

CPC分类号： H01L21/67248 ,  G01K1/026 ,  G01K1/14 ,  G01K7/00 ,  H01L21/67103 ,  H01L21/67109 ,  H01L21/67346 ,  H01L21/6833

摘要： A substrate holder includes a base plate, a bond layer disposed over the base plate, and a ceramic layer disposed over the bond layer. The ceramic layer has a top surface including an area configured to support a substrate. A number of temperature measurement electrical devices are attached to the ceramic layer. Electrically conductive traces are embedded within the ceramic layer and positioned and routed to electrically connect with one or more of electrical contacts of the number of temperature measurement electrical devices. Electrical wires are disposed to electrically contact the electrically conductive traces. The electrical wires extend from the ceramic layer through the bond layer and through the base plate to a control circuit.

公开(公告)号：US09012243B2

公开(公告)日：2015-04-21

申请号：US14470544

申请日：2014-08-27

申请人： Lam Research Corporation

发明人： Yoshie Kimura ,  Tom Kamp ,  Eric Pape ,  Rohit DeshPande ,  Keith Gaff ,  Gowri Kamarthy

IPC分类号： H01L21/66 ,  H01L21/67 ,  H01J37/32

CPC分类号： H01L22/26 ,  H01J37/32724 ,  H01J37/32926 ,  H01J37/32935 ,  H01L21/67069 ,  H01L21/67248 ,  H01L22/12 ,  H01L22/20 ,  H01L2924/0002 ,  H01L2924/00

摘要： Exemplary embodiments are directed to controlling CD uniformity of a wafer by controlling trim time on temperature in a plasma processing system. The plasma processing system has a wafer support assembly including a plurality of independently controllable temperature control zones across a chuck and a controller that controls each temperature control zone. The controller receives process control and temperature data associated with at least one wafer previously processed in a plasma chamber of the plasma processing system. The controller also receives critical device parameters of a current wafer to be processed in the plasma chamber. The controller calculates a target trim time and a target temperature profile of the current wafer based on the process control and temperature data of the at least one previously processed wafers and the critical device parameters of the current wafer. The current wafer as subjected to a trimming operation for a duration of the target trim time while controlling temperatures in the temperature control zones to thereby control temperature of each device die location based on the target temperature profile.

摘要翻译： 示例性实施例涉及通过控制等离子体处理系统中的温度调节时间来控制晶片的CD均匀性。 等离子体处理系统具有晶片支撑组件，其包括横跨卡盘的多个可独立控制的温度控制区域和控制每个温度控制区域的控制器。 控制器接收与先前在等离子体处理系统的等离子体室中处理的至少一个晶片相关联的过程控制和温度数据。 控制器还接收等离子体室中要处理的当前晶片的关键器件参数。 控制器基于至少一个先前处理的晶片的过程控制和温度数据以及当前晶片的关键器件参数来计算当前晶片的目标修整时间和目标温度分布。 当前的晶片在控制温度控制区域中的温度的同时进行修整操作，同时控制温度控制区域中的温度，从而基于目标温度分布来控制每个器件管芯位置的温度。

公开(公告)号：US08852964B2

公开(公告)日：2014-10-07

申请号：US13758266

申请日：2013-02-04

申请人： Lam Research Corporation

发明人： Yoshie Kimura ,  Tom Kamp ,  Eric Pape ,  Rohit DeshPande ,  Keith Gaff ,  Gowri Kamarthy

IPC分类号： H01L21/00 ,  H01L21/67 ,  H01L21/66

CPC分类号： H01L22/26 ,  H01J37/32724 ,  H01J37/32926 ,  H01J37/32935 ,  H01L21/67069 ,  H01L21/67248 ,  H01L22/12 ,  H01L22/20 ,  H01L2924/0002 ,  H01L2924/00

摘要： Exemplary embodiments are directed to controlling CD uniformity of a wafer by controlling trim time on temperature in a plasma processing system. The plasma processing system has a wafer support assembly including a plurality of independently controllable temperature control zones across a chuck and a controller that controls each temperature control zone. The controller receives process control and temperature data associated with at least one wafer previously processed in a plasma chamber of the plasma processing system, and critical device parameters of a current wafer to be processed in the plasma chamber. The controller calculates a target trim time and a target temperature profile of the current wafer based on the process control and temperature data, and the critical device parameters. The current wafer is trimmed during the target trim time while the temperature of each device die location is controlled based on the target temperature profile.

摘要翻译： 示例性实施例涉及通过控制等离子体处理系统中的温度调节时间来控制晶片的CD均匀性。 等离子体处理系统具有晶片支撑组件，其包括横跨卡盘的多个可独立控制的温度控制区域和控制每个温度控制区域的控制器。 控制器接收与先前在等离子体处理系统的等离子体室中处理的至少一个晶片相关联的过程控制和温度数据，以及在等离子体室中待处理的当前晶片的关键器件参数。 控制器基于过程控制和温度数据以及关键设备参数来计算当前晶片的目标修整时间和目标温度分布。 在目标修整时间期间修剪当前晶片，同时基于目标温度分布来控制每个器件管芯位置的温度。

公开(公告)号：US12060636B2

公开(公告)日：2024-08-13

申请号：US17273649

申请日：2019-09-16

申请人： LAM RESEARCH CORPORATION

发明人： Chiara Helena Catherina Giammanco MacPherson ,  Eric Pape

IPC分类号： C23C16/40 ,  C23C16/02 ,  C23C16/44 ,  C23C16/455 ,  H01L21/02 ,  H01L21/683

CPC分类号： C23C16/401 ,  C23C16/0245 ,  C23C16/4404 ,  C23C16/45557 ,  H01L21/02046 ,  H01L21/02315 ,  H01L21/6833

摘要： A method for conditioning a plasma processing chamber including a chuck is provided. The method comprises a plurality of cycles, wherein each cycle comprises cleaning an interior of the plasma processing chamber and the chuck and forming a silicon oxide based coating on the interior of the plasma processing chamber and the chuck. The silicon oxide based coating has a first layer and a second layer.