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公开(公告)号：US08772941B2
公开(公告)日：2014-07-08
申请号：US12206314
申请日：2008-09-08
IPC分类号： H01L23/522
CPC分类号： H01L21/76808 , H01L21/7682
摘要： A method for manufacturing a circuit includes the step of providing a first wiring level comprising first wiring level conductors separated by a first wiring level dielectric material. A first dielectric layer with a plurality of interconnect openings and a plurality of gap openings is formed above the first wiring level. The interconnect openings and the gap openings are pinched off with a pinching dielectric material to form relatively low dielectric constant (low-k) volumes in the gap openings. Metallic conductors comprising second wiring level conductors and interconnects to the first wiring level conductors are formed at the interconnect openings while maintaining the relatively low-k volumes in the gap openings. The gap openings with the relatively low-k volumes reduce parasitic capacitance between adjacent conductor structures formed by the conductors and interconnects.
摘要翻译： 一种制造电路的方法包括提供包括由第一布线层介电材料分隔开的第一布线层导体的第一布线层的步骤。 具有多个互连开口和多个间隙开口的第一介电层形成在第一布线层的上方。 互连开口和间隙开口用夹持电介质材料夹紧，以在间隙开口中形成相对较低的介电常数（低k）体积。 包括第二布线层导体的金属导体和与第一布线层导体的互连形成在互连开口处，同时保持间隙开口中相对低的k体积。 具有相对低k体积的间隙开口减小由导体和互连件形成的相邻导体结构之间的寄生电容。
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2.发明授权Microelectronic circuit structure with layered low dielectric constant regions 失效微电子电路结构具有层状低介电常数区域公开(公告)号：US07692308B2
公开(公告)日：2010-04-06
申请号：US12256735
申请日：2008-10-23
IPC分类号： H01L29/40
CPC分类号： H01L21/7682 , H01L21/76808 , H01L21/76835 , H01L23/5222 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： The circuit structure includes at least two generally parallel conductor structures, and a plurality of substantially horizontal layers of layer dielectric material interspersed with substantially horizontally extending relatively low dielectric constant (low-k) volumes. The substantially horizontal layers and the substantially horizontally extending volumes are generally interposed between the at least two generally parallel conductor structures. Also included are a plurality of substantially vertically extending relatively low-k volumes sealed within the substantially horizontal layers and the substantially horizontally extending volumes between the at least two generally parallel conductor structures. The substantially vertically extending relatively low-k volumes and the substantially horizontally extending relatively low-k volumes reduce parasitic capacitance between the at least two generally parallel conductor structures as compared to an otherwise comparable microelectronic circuit not including the relatively low-k volumes.
摘要翻译： 电路结构包括至少两个大致平行的导体结构，以及多个基本上水平的层介质材料层，散布着基本上水平延伸的相对较低的介电常数（低k）体积。 基本水平的层和基本上水平延伸的体积通常介于至少两个大致平行的导体结构之间。 还包括在基本水平的层内密封的多个基本上垂直延伸的相对低k的体积，以及在至少两个大致平行的导体结构之间的基本水平延伸的体积。 与不包括相对低k体积的其他可比较的微电子电路相比，基本垂直延伸的相对低k体积和基本水平延伸的相对低k体积减小了至少两个大致平行的导体结构之间的寄生电容。
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3.发明申请MICROELECTRONIC CIRCUIT STRUCTURE WITH LAYERED LOW DIELECTRIC CONSTANT REGIONS 失效具有层状低介电常数区域的微电路电路结构公开(公告)号：US20090072410A1
公开(公告)日：2009-03-19
申请号：US12256735
申请日：2008-10-23
IPC分类号： H01L23/52
CPC分类号： H01L21/7682 , H01L21/76808 , H01L21/76835 , H01L23/5222 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： The circuit structure includes at least two generally parallel conductor structures, and a plurality of substantially horizontal layers of layer dielectric material interspersed with substantially horizontally extending relatively low dielectric constant (low-k) volumes. The substantially horizontal layers and the substantially horizontally extending volumes are generally interposed between the at least two generally parallel conductor structures. Also included are a plurality of substantially vertically extending relatively low-k volumes sealed within the substantially horizontal layers and the substantially horizontally extending volumes between the at least two generally parallel conductor structures. The substantially vertically extending relatively low-k volumes and the substantially horizontally extending relatively low-k volumes reduce parasitic capacitance between the at least two generally parallel conductor structures as compared to an otherwise comparable microelectronic circuit not including the relatively low-k volumes.
摘要翻译： 电路结构包括至少两个大致平行的导体结构，以及多个基本上水平的层介质材料层，散布着基本上水平延伸的相对较低的介电常数（低k）体积。 基本水平的层和基本上水平延伸的体积通常介于至少两个大致平行的导体结构之间。 还包括在基本水平的层内密封的多个基本上垂直延伸的相对低k的体积，以及在至少两个大致平行的导体结构之间的基本水平延伸的体积。 与不包括相对低k体积的其他可比较的微电子电路相比，基本垂直延伸的相对低k体积和基本水平延伸的相对低k体积减小了至少两个大致平行的导体结构之间的寄生电容。
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4.发明授权Circuit structure with low dielectric constant regions and method of forming same 有权具有低介电常数区域的电路结构及其形成方法公开(公告)号：US07439172B2
公开(公告)日：2008-10-21
申请号：US11623478
申请日：2007-01-16
IPC分类号： H01L21/4763
CPC分类号： H01L21/76808 , H01L21/7682
摘要： A method for manufacturing a circuit includes the step of providing a first wiring level comprising first wiring level conductors separated by a first wiring level dielectric material. A first dielectric layer with a plurality of interconnect openings and a plurality of gap openings is formed above the first wiring level. The interconnect openings and the gap openings are pinched off with a pinching dielectric material to form relatively low dielectric constant (low-k) volumes in the gap openings. Metallic conductors comprising second wiring level conductors and interconnects to the first wiring level conductors are formed at the interconnect openings while maintaining the relatively low-k volumes in the gap openings. The gap openings with the relatively low-k volumes reduce parasitic capacitance between adjacent conductor structures formed by the conductors and interconnects.
摘要翻译： 一种制造电路的方法包括提供包括由第一布线层介电材料分隔开的第一布线层导体的第一布线层的步骤。 具有多个互连开口和多个间隙开口的第一介电层形成在第一布线层的上方。 互连开口和间隙开口用夹持电介质材料夹紧，以在间隙开口中形成相对较低的介电常数（低k）体积。 包括第二布线层导体的金属导体和与第一布线层导体的互连形成在互连开口处，同时保持间隙开口中相对低的k体积。 具有相对低k体积的间隙开口减小由导体和互连件形成的相邻导体结构之间的寄生电容。
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5.发明申请Circuit Structure with Low Dielectric Constant Regions and Method of Forming Same 有权具有低介电常数区域的电路结构及其形成方法公开(公告)号：US20080171432A1
公开(公告)日：2008-07-17
申请号：US11623478
申请日：2007-01-16
IPC分类号： H01L21/4763
CPC分类号： H01L21/76808 , H01L21/7682
摘要： A method for manufacturing a circuit includes the step of providing a first wiring level comprising first wiring level conductors separated by a first wiring level dielectric material. A first dielectric layer with a plurality of inter connect openings and a plurality of gap openings is formed above the first wiring level. The interconnect openings and the gap openings are pinched off with a pinching dielectric material to form relatively low dielectric constant (low-k) volumes in the gap openings. Metallic conductors comprising second wiring level conductors and interconnects to the first wiring level conductors are formed at the interconnect openings while maintaining the relatively low-k volumes in the gap openings. The gap openings with the relatively low-k volumes reduce parasitic capacitance between adjacent conductor structures formed by the conductors and interconnects.
摘要翻译： 一种制造电路的方法包括提供包括由第一布线层介电材料分隔开的第一布线层导体的第一布线层的步骤。 具有多个互连开口和多个间隙开口的第一电介质层形成在第一布线层的上方。 互连开口和间隙开口用夹持电介质材料夹紧，以在间隙开口中形成相对较低的介电常数（低k）体积。 包括第二布线层导体的金属导体和与第一布线层导体的互连形成在互连开口处，同时保持间隙开口中相对低的k体积。 具有相对低k体积的间隙开口减小由导体和互连件形成的相邻导体结构之间的寄生电容。
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6.发明授权Microelectronic circuit structure with layered low dielectric constant regions and method of forming same 失效具有层状低介电常数区域的微电子电路结构及其形成方法公开(公告)号：US07485567B2
公开(公告)日：2009-02-03
申请号：US11670524
申请日：2007-02-02
IPC分类号： H01L21/4763
CPC分类号： H01L21/7682 , H01L21/76808 , H01L21/76835 , H01L23/5222 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A method for manufacturing a microelectronic circuit includes the steps of providing a first wiring level comprising first wiring level conductors separated by a first wiring level dielectric material; forming a plurality of alternating layers of layer dielectric material and sacrificial material over the first wiring level; and forming a plurality of interconnect openings and a plurality of gap openings in the alternating layers of layer dielectric material and sacrificial material. The interconnect openings are formed over the first wiring level conductors. The method further includes forming (i) metallic conductors comprising second wiring level conductors, and (ii) interconnects, at the interconnect openings; and removing the layers of the sacrificial material through the gap openings.
摘要翻译： 一种制造微电子电路的方法包括以下步骤：提供包括由第一布线层介电材料隔开的第一布线层导体的第一布线层; 在所述第一布线层上形成层状介电材料和牺牲材料的多个交替层; 以及在层介电材料和牺牲材料的交替层中形成多个互连开口和多个间隙开口。 互连开口形成在第一布线层导体上。 该方法还包括形成（i）包括第二布线层导体的金属导体，和（ii）互连开口处的互连; 并且通过间隙开口去除牺牲材料的层。
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公开(公告)号：US20090008791A1
公开(公告)日：2009-01-08
申请号：US12206314
申请日：2008-09-08
IPC分类号： H01L23/522
CPC分类号： H01L21/76808 , H01L21/7682
摘要： A method for manufacturing a circuit includes the step of providing a first wiring level comprising first wiring level conductors separated by a first wiring level dielectric material. A first dielectric layer with a plurality of interconnect openings and a plurality of gap openings is formed above the first wiring level. The interconnect openings and the gap openings are pinched off with a pinching dielectric material to form relatively low dielectric constant (low-k) volumes in the gap openings. Metallic conductors comprising second wiring level conductors and interconnects to the first wiring level conductors are formed at the interconnect openings while maintaining the relatively low-k volumes in the gap openings. The gap openings with the relatively low-k volumes reduce parasitic capacitance between adjacent conductor structures formed by the conductors and interconnects.
摘要翻译： 一种制造电路的方法包括提供包括由第一布线层介电材料分隔开的第一布线层导体的第一布线层的步骤。 具有多个互连开口和多个间隙开口的第一介电层形成在第一布线层的上方。 互连开口和间隙开口用夹持电介质材料夹紧，以在间隙开口中形成相对较低的介电常数（低k）体积。 包括第二布线层导体的金属导体和与第一布线层导体的互连形成在互连开口处，同时保持间隙开口中相对低的k体积。 具有相对低k体积的间隙开口减小了由导体和互连件形成的相邻导体结构之间的寄生电容。
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8.发明申请Microelectronic Circuit Structure With Layered Low Dielectric Constant Regions And Method Of Forming Same 失效具有层状低介电常数区域的微电子电路结构及其形成方法公开(公告)号：US20080185728A1
公开(公告)日：2008-08-07
申请号：US11670524
申请日：2007-02-02
IPC分类号： H01L23/48 , H01L21/4763
CPC分类号： H01L21/7682 , H01L21/76808 , H01L21/76835 , H01L23/5222 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A method for manufacturing a microelectronic circuit includes the steps of providing a first wiring level comprising first wiring level conductors separated by a first wiring level dielectric material; forming a plurality of alternating layers of layer dielectric material and sacrificial material over the first wiring level; and forming a plurality of interconnect openings and a plurality of gap openings in the alternating layers of layer dielectric material and sacrificial material. The interconnect openings are formed over the first wiring level conductors. The method further includes forming (i) metallic conductors comprising second wiring level conductors, and (ii) interconnects, at the interconnect openings; and removing the layers of the sacrificial material through the gap openings.
摘要翻译： 一种制造微电子电路的方法包括以下步骤：提供包括由第一布线层介电材料隔开的第一布线层导体的第一布线层; 在所述第一布线层上形成层状介电材料和牺牲材料的多个交替层; 以及在层介电材料和牺牲材料的交替层中形成多个互连开口和多个间隙开口。 互连开口形成在第一布线层导体上。 该方法还包括形成（i）包括第二布线层导体的金属导体，和（ii）互连开口处的互连; 并且通过间隙开口去除牺牲材料的层。
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公开(公告)号：US07906428B2
公开(公告)日：2011-03-15
申请号：US12121216
申请日：2008-05-15
申请人： Lawrence A. Clevenger , Timothy Joseph Dalton , Louis C. Hsu , Conal Eugene Murray , Carl Radens , Kwong-Hon Wong , Chih-Chao Yang
发明人： Lawrence A. Clevenger , Timothy Joseph Dalton , Louis C. Hsu , Conal Eugene Murray , Carl Radens , Kwong-Hon Wong , Chih-Chao Yang
IPC分类号： H01L21/4763
CPC分类号： H01L21/76802 , H01L21/76805 , H01L21/76843 , H01L21/76844 , H01L21/76847 , H01L21/76865 , H01L23/5226 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： The present invention provides an interconnect structure that can be made in the BEOL which exhibits good mechanical contact during normal chip operations and does not fail during various reliability tests as compared with the conventional interconnect structures described above. The inventive interconnect structure has a kinked interface at the bottom of a via that is located within an interlayer dielectric layer. Specifically, the inventive interconnect structure includes a first dielectric layer having at least one metallic interconnect embedded within a surface thereof; a second dielectric layer located atop the first dielectric layer, wherein said second dielectric layer has at least one aperture having an upper line region and a lower via region, wherein the lower via region includes a kinked interface; at least one pair of liners located on at least vertical walls of the at least one aperture; and a conductive material filling the at least one aperture.
摘要翻译： 本发明提供一种可以在BEOL中制造的互连结构，其在正常的芯片操作期间表现出良好的机械接触，并且在与上述的常规互连结构相比在各种可靠性测试期间不会失败。 本发明的互连结构在通孔的底部具有位于层间介质层内的扭结界面。 具体地，本发明的互连结构包括：第一介电层，其具有嵌入在其表面内的至少一个金属互连; 位于所述第一介电层顶部的第二电介质层，其中所述第二电介质层具有至少一个具有上线区域和下通孔区域的孔，其中所述下通孔区域包括扭结界面; 位于所述至少一个孔的至少垂直壁上的至少一对衬垫; 以及填充所述至少一个孔的导电材料。
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公开(公告)号：US07528065B2
公开(公告)日：2009-05-05
申请号：US11333068
申请日：2006-01-17
申请人： Lawrence A. Clevenger , Timothy J. Dalton , Louis C. Hsu , Carl Radens , Kwong-Hon Wong , Chih-Chao Yang
发明人： Lawrence A. Clevenger , Timothy J. Dalton , Louis C. Hsu , Carl Radens , Kwong-Hon Wong , Chih-Chao Yang
IPC分类号： H01L21/4763
CPC分类号： H01L27/1203 , H01L21/28114 , H01L21/823456 , H01L21/84 , H01L29/42376 , H01L2924/0002 , H01L2924/00
摘要： A transistor device and method of forming the same comprises a substrate; a first gate electrode over the substrate; a second gate electrode over the substrate; and a landing pad comprising a pair of flanged ends overlapping the second gate electrode, wherein the structure of the second gate electrode is discontinuous with the structure of the landing pad.
摘要翻译： 晶体管器件及其形成方法包括：衬底; 衬底上的第一栅电极; 在所述衬底上方的第二栅电极; 以及着陆垫，其包括与所述第二栅电极重叠的一对凸缘端，其中所述第二栅极的结构与所述着陆焊盘的结构不连续。
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