摘要:
An interconnect structure in which the adhesion between an upper level low-k dielectric material, such as a material comprising elements of Si, C, O, and H, and an underlying diffusion capping dielectric, such as a material comprising elements of C, Si, N and H, is improved by incorporating an adhesion transition layer between the two dielectric layers. The presence of the adhesion transition layer between the upper level low-k dielectric and the diffusion barrier capping dielectric can reduce the chance of delamination of the interconnect structure during the packaging process. The adhesion transition layer provided herein includes a lower SiOx- or SiON-containing region and an upper C graded region. Methods of forming such a structure, in particularly the adhesion transition layer, are also provided.
摘要翻译:一种互连结构,其中上层低k介电材料(例如包含Si,C,O和H的元素的材料)与下面的扩散覆盖电介质(例如包含C,Si元素的材料)之间的粘合 通过在两个电介质层之间引入粘附过渡层来改善N和H。 在上层低k电介质和扩散阻挡覆盖电介质之间的粘附过渡层的存在可以减少在包装过程中互连结构的分层的可能性。 本文提供的粘合过渡层包括含低级SiO x - 或SiON的区域和上C级分区域。 还提供了形成这种结构,特别是粘附过渡层的方法。
摘要:
An interconnect structure in which the adhesion between an upper level low-k dielectric material, such as a material comprising elements of Si, C, O, and H, and an underlying diffusion capping dielectric, such as a material comprising elements of C, Si, N and H, is improved by incorporating an adhesion transition layer between the two dielectric layers. The presence of the adhesion transition layer between the upper level low-k dielectric and the diffusion barrier capping dielectric can reduce the chance of delamination of the interconnect structure during the packaging process. The adhesion transition layer provided herein includes a lower SiOx— or SiON-containing region and an upper C graded region. Methods of forming such a structure, in particularly the adhesion transition layer, are also provided.
摘要翻译:一种互连结构,其中上层低k介电材料(例如包含Si,C,O和H的元素的材料)与下面的扩散覆盖电介质(例如包含C,Si元素的材料)之间的粘合 通过在两个电介质层之间引入粘附过渡层来改善N和H。 在上层低k电介质和扩散阻挡覆盖电介质之间的粘附过渡层的存在可以减少在包装过程中互连结构的分层的可能性。 本文提供的粘合过渡层包括含低级SiO x - 或SiON的区域和上C级分区域。 还提供了形成这种结构,特别是粘附过渡层的方法。
摘要:
An interconnect structure in which the adhesion between an upper level low-k dielectric material, such as a material comprising elements of Si, C, O, and H, and an underlying diffusion capping dielectric, such as a material comprising elements of C, Si, N and H, is improved by incorporating an adhesion transition layer between the two dielectric layers. The presence of the adhesion transition layer between the upper level low-k dielectric and the diffusion barrier capping dielectric can reduce the chance of delamination of the interconnect structure during the packaging process. The adhesion transition layer provided herein includes a lower SiOx— or SiON-containing region and an upper C graded region. Methods of forming such a structure, in particularly the adhesion transition layer, are also provided.
摘要:
An interconnect structure in which the adhesion between an upper level low-k dielectric material, such as a material comprising elements of Si, C, O, and H, and an underlying diffusion capping dielectric, such as a material comprising elements of C, Si, N and H, is improved by incorporating an adhesion transition layer between the two dielectric layers. The presence of the adhesion transition layer between the upper level low-k dielectric and the diffusion barrier capping dielectric can reduce the chance of delamination of the interconnect structure during the packaging process. The adhesion transition layer provided herein includes a lower SiOx- or SiON-containing region and an upper C graded region. Methods of forming such a structure, in particularly the adhesion transition layer, are also provided.
摘要翻译:一种互连结构,其中上层低k介电材料(例如包含Si,C,O和H的元素的材料)与下面的扩散覆盖电介质(例如包含C,Si元素的材料)之间的粘合 通过在两个电介质层之间引入粘附过渡层来改善N和H。 在上层低k电介质和扩散阻挡覆盖电介质之间的粘附过渡层的存在可以减少在包装过程中互连结构的分层的可能性。 本文提供的粘合过渡层包括含低级SiO x - 或SiON的区域和上C级分区域。 还提供了形成这种结构,特别是粘附过渡层的方法。
摘要:
A chip is provided which includes a back-end-of-line (“BEOL”) interconnect structure. The BEOL interconnect structure includes a plurality of interlevel dielectric (“ILD”) layers which include a dielectric material curable by ultraviolet (“UV”) radiation. A plurality of metal interconnect wiring layers are embedded in the plurality of ILD layers. Dielectric barrier layers cover the plurality of metal interconnect wiring layers, the dielectric barrier layers being adapted to reduce diffusion of materials between the metal interconnect wiring layers and the ILD layers. One of more of the dielectric barrier layers is adapted to retain compressive stress while withstanding UV radiation sufficient to cure the dielectric material of the ILD layers, making the BEOL structure better capable of avoiding deformation due to thermal and/or mechanical stress.
摘要:
A chip is provided which includes a back-end-of-line (“BEOL”) interconnect structure. The BEOL interconnect structure includes a plurality of interlevel dielectric (“ILD”) layers which include a dielectric material curable by ultraviolet (“UV”) radiation. A plurality of metal interconnect wiring layers are embedded in the plurality of ILD layers. Dielectric barrier layers cover the plurality of metal interconnect wiring layers, the dielectric barrier layers being adapted to reduce diffusion of materials between the metal interconnect wiring layers and the ILD layers. One of more of the dielectric barrier layers is adapted to retain compressive stress while withstanding UV radiation sufficient to cure the dielectric material of the ILD layers, making the BEOL structure better capable of avoiding deformation due to thermal and/or mechanical stress.
摘要:
The present invention provides an interconnect structure (of the single or dual damascene type) and a method of forming the same, in which a dense (i.e., non-porous) dielectric spacer is present on the sidewalls of a dielectric material. More specifically, the inventive structure includes a dielectric material having a conductive material embedded within at least one opening in the dielectric material, wherein the conductive material is laterally spaced apart from the dielectric material by a diffusion barrier, a dense dielectric spacer and, optionally, an air gap. The presence of the dense dielectric spacer results in a hybrid interconnect structure that has improved reliability and performance as compared with existing prior art interconnect structures which do not include such dense dielectric spacers. Moreover, the inventive hybrid interconnect structure provides for better process control which leads to the potential for high volume manufacturing.
摘要:
A redundant metal diffusion barrier is provided for an interconnect structure which improves the reliability and extendibility of the interconnect structure. The redundant metal diffusion barrier layer is located within an opening that is located within a dielectric material and it is between a diffusion barrier layer and a conductive material which are also present within the opening. The redundant diffusion barrier includes a single layered or multilayered structure comprising Ru and a Co-containing material including pure Co or a Co alloy including at least one of N, B and P.
摘要:
A method patterns at least one opening in a low-K insulator layer of a multi-level integrated circuit structure, such that a copper conductor is exposed at the bottom of the opening. The method then lines the sidewalls and the bottom of the opening with a first Tantalum Nitride layer in a first chamber and forms a Tantalum layer on the first Tantalum Nitride layer in the first chamber. Next, sputter etching on the opening is performed in the first chamber, so as to expose the conductor at the bottom of the opening. A second Tantalum Nitride layer is formed on the conductor, the Tantalum layer, and the first Tantalum Nitride layer, again in the first chamber. After the second Tantalum Nitride layer is formed, the methods herein form a flash layer comprising a Platinum group metal on the second Tantalum Nitride layer in a second, different chamber.
摘要:
A redundant metal diffusion barrier is provided for an interconnect structure which improves the reliability and extendibility of the interconnect structure. The redundant metal diffusion barrier layer is located within an opening that is located within a dielectric material and it is between a diffusion barrier layer and a conductive material which are also present within the opening. The redundant diffusion barrier includes a single layered or multilayered structure comprising Ru and a Co-containing material including pure Co or a Co alloy including at least one of N, B and P.