公开(公告)号：US20050116342A1

公开(公告)日：2005-06-02

申请号：US11024067

申请日：2004-12-28

申请人： Lawrence Clevenger ,  Ronald Filippi ,  Mark Hoinkis ,  Jeffery Hurd ,  Roy Iggulden ,  Herbert Palm ,  Hans Poetzlberger ,  Kenneth Rodbell ,  Florian Schnabel ,  Stefan Weber ,  Ebrahim Mehter

发明人： Lawrence Clevenger ,  Ronald Filippi ,  Mark Hoinkis ,  Jeffery Hurd ,  Roy Iggulden ,  Herbert Palm ,  Hans Poetzlberger ,  Kenneth Rodbell ,  Florian Schnabel ,  Stefan Weber ,  Ebrahim Mehter

IPC分类号： H01L21/28 ,  H01L21/768 ,  H01L23/485 ,  H01L23/532 ,  H01L21/44 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L21/76843 ,  H01L21/76807 ,  H01L21/76849 ,  H01L21/76876 ,  H01L23/485 ,  H01L23/53223 ,  H01L2924/0002 ,  H01L2924/00

摘要： A conductor for interconnecting integrated circuit components having improved reliability. The conductor includes a liner surrounding at least three surfaces of the conductor, producing a low textured conductor. It has been found that low textured conductor results in improved electromigration lifetime.

公开(公告)号：US20060254053A1

公开(公告)日：2006-11-16

申请号：US10908392

申请日：2005-05-10

申请人： Kaushik Chanda ,  James Demarest ,  Ronald Filippi ,  Roy Iggulden ,  Edward Kiewra ,  Ping-Chuan Wang ,  Yun-Yu Wang

发明人： Kaushik Chanda ,  James Demarest ,  Ronald Filippi ,  Roy Iggulden ,  Edward Kiewra ,  Ping-Chuan Wang ,  Yun-Yu Wang

IPC分类号： H05K3/02 ,  H01K3/10 ,  B24B1/00

CPC分类号： B24B37/042 ,  H01L21/31144 ,  H01L21/76834 ,  H01L21/7684 ,  H01L21/76849 ,  H01L21/76852 ,  H01L21/76885 ,  Y10T29/49156 ,  Y10T29/49165 ,  Y10T29/49204

摘要： Disclosed are a damascene and dual damascene processes both of which incorporate the use of a release layer to remove trace amounts of residual material between metal interconnect lines. The release layer is deposited onto a dielectric layer. The release layer comprises an organic material, a dielectric material, a metal or a metal nitride. Trenches are etched into the dielectric layer. The trenches are lined with a liner and filled with a conductor. The conductor and liner materials are polished off the release layer. However, trace amounts of the residual material may remain. The release layer is removed (e.g., by an appropriate solvent or wet etching process) to remove the residual material. If the trench is formed such that the release layer overlaps the walls of the trench, then when the release layer is removed another dielectric layer can be deposited that reinforces the corners around the top of the metal interconnect line.

摘要翻译： 公开了一种镶嵌和双镶嵌工艺，其中两者都结合使用剥离层以在金属互连线之间移除痕量的残余材料。 释放层沉积在电介质层上。 释放层包括有机材料，电介质材料，金属或金属氮化物。 沟槽蚀刻到电介质层中。 沟槽内衬衬里，填充导体。 导体和衬里材料从剥离层抛光。 然而，痕量的剩余材料可能会残留。 去除脱模层（例如，通过适当的溶剂或湿蚀刻工艺）以除去残留的材料。 如果沟槽形成为使得剥离层与沟槽的壁重叠，则当除去剥离层时，可以沉积另外的介电层，加强围绕金属互连线的顶部的拐角。

公开(公告)号：US20060073695A1

公开(公告)日：2006-04-06

申请号：US10711697

申请日：2004-09-30

申请人： Ronald Filippi ,  Roy Iggulden ,  Edward Kiewra ,  Ping-Chuan Wang

发明人： Ronald Filippi ,  Roy Iggulden ,  Edward Kiewra ,  Ping-Chuan Wang

IPC分类号： H01L21/4763 ,  H01L21/311

CPC分类号： H01L21/7682 ,  H01L21/76807 ,  H01L21/76831 ,  H01L23/5222 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： Methods of forming a gas dielectric structure for a semiconductor structure by using a sacrificial layer. In particular, one embodiment of the invention includes forming an opening for semiconductor structure in a dielectric layer on a substrate; depositing a sacrificial layer over the opening; performing a directional etch on the sacrificial layer to form a sacrificial layer sidewall on the opening; depositing a conductive liner over the opening; depositing a metal in the opening; planarizing the metal and the conductive liner; removing the sacrificial layer sidewall to form a void; and depositing a cap layer over the void to form the gas dielectric structure. The invention is easily implemented in damascene wire formation processes, and improves structural stability.

摘要翻译： 通过使用牺牲层形成用于半导体结构的气体电介质结构的方法。 特别地，本发明的一个实施例包括在基板上的电介质层中形成用于半导体结构的开口; 在开口上沉积牺牲层; 在所述牺牲层上执行定向蚀刻以在所述开口上形成牺牲层侧壁; 在所述开口上沉积导电衬垫; 在开口中沉积金属; 平面化金属和导电衬垫; 去除牺牲层侧壁以形成空隙; 以及在所述空隙上沉积盖层以形成气体介电结构。 本发明易于在镶嵌线形成过程中实现，并提高结构稳定性。

公开(公告)号：US20060066314A1

公开(公告)日：2006-03-30

申请号：US10711641

申请日：2004-09-29

申请人： Ishtiaq Ahsan ,  Ronald Filippi ,  Roy Iggulden ,  Edward Kiewra ,  Ping-Chuan Wang

发明人： Ishtiaq Ahsan ,  Ronald Filippi ,  Roy Iggulden ,  Edward Kiewra ,  Ping-Chuan Wang

IPC分类号： G01R31/08

CPC分类号： H01L22/34 ,  G01R31/2858 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method and apparatus for detecting metal extrusion associated with electromigration (EM) under high current density situations within an EM test line by measuring changes in capacitance associated with metal extrusion that occurs in the vicinity of the charge carrying surfaces of one or more capacitors situated in locations of close physical proximity to anticipated sites of metal extrusion on an EM test line are provided. The capacitance of each of the one or more capacitors is measured prior to and then during or after operation of the EM test line so as to detect capacitance changes indicating metal extrusion.

摘要翻译： 一种用于在EM测试线中的高电流密度情况下检测与电迁移（EM）有关的金属挤出的方法和装置，其通过测量在位于一个或多个电容器中的一个或多个电容器的电荷承载表面附近的与金属挤出相关的电容的变化 提供了在EM测试线上与金属挤压的预期位置紧密物理接近的位置。 一个或多个电容器中的每一个的电容在EM测试线之前和之后测量，以便检测指示金属挤压的电容变化。

公开(公告)号：US20070120259A1

公开(公告)日：2007-05-31

申请号：US11669180

申请日：2007-01-31

申请人： Ronald Filippi ,  Roy Iggulden ,  Edward Kiewra ,  Stephen Loh ,  Ping-Chuan Wang

发明人： Ronald Filippi ,  Roy Iggulden ,  Edward Kiewra ,  Stephen Loh ,  Ping-Chuan Wang

IPC分类号： H01L23/52

CPC分类号： H01L21/7684 ,  H01L21/3212 ,  H01L21/7688 ,  H01L22/24 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method and structure for the detection of residual liner materials after polishing in a damascene processes includes an integrated circuit comprising a substrate; a dielectric layer over the substrate; a marker layer over the dielectric layer; a liner over the marker layer and dielectric layer; and a metal layer over the liner, wherein the marker layer comprises ultraviolet detectable material, which upon excitation by an ultraviolet ray signals an absence of the metal layer and the liner over the marker layer. Moreover, the marker layer comprises a separate layer from the dielectric layer. Additionally, the ultraviolet detectable material comprises fluorescent material or phosphorescent material.

摘要翻译： 用于在镶嵌工艺中抛光之后检测残留衬垫材料的方法和结构包括：包括衬底的集成电路; 介电层; 电介质层上的标记层; 标记层和电介质层上的衬垫; 以及在所述衬里上的金属层，其中所述标记层包括紫外线可检测材料，其在通过紫外线激发时表示在所述标记层上不存在所述金属层和所述衬垫。 此外，标记层包括与电介质层分离的层。 另外，紫外线可检测材料包括荧光材料或磷光材料。

公开(公告)号：US20070158851A1

公开(公告)日：2007-07-12

申请号：US11306825

申请日：2006-01-12

申请人： Kaushik Chanda ,  James Demarest ,  Ronald Filippi ,  Roy Iggulden ,  Edward Kiewra ,  Vincent McGahay ,  Ping-Chuan Wang ,  Yun-Yu Wang

发明人： Kaushik Chanda ,  James Demarest ,  Ronald Filippi ,  Roy Iggulden ,  Edward Kiewra ,  Vincent McGahay ,  Ping-Chuan Wang ,  Yun-Yu Wang

IPC分类号： H01L21/4763 ,  H01L23/48

CPC分类号： H01L23/53238 ,  H01L21/76846 ,  H01L23/5283 ,  H01L2924/0002 ,  H01L2924/00

摘要： In the back end of an integrated circuit employing dual-damascene interconnects, the interconnect members have a first non-conformal liner that has a thicker portion at the top of the trench level of the interconnect; and a conformal second liner that combines with the first liner to block diffusion of the metal fill material.

摘要翻译： 在采用双镶嵌互连的集成电路的后端中，互连构件具有第一非保形衬套，其在互连的沟槽级的顶部具有较厚的部分; 以及与第一衬垫结合以阻挡金属填充材料的扩散的共形第二衬垫。

公开(公告)号：US20070267386A1

公开(公告)日：2007-11-22

申请号：US11833283

申请日：2007-08-03

申请人： Kaushik Chanda ,  James Demarest ,  Ronald Filippi ,  Roy Iggulden ,  Edward Kiewra ,  Ping-Chuan Wang ,  Yun-Yu Wang

发明人： Kaushik Chanda ,  James Demarest ,  Ronald Filippi ,  Roy Iggulden ,  Edward Kiewra ,  Ping-Chuan Wang ,  Yun-Yu Wang

IPC分类号： H01B13/00 ,  B44C1/22

CPC分类号： B24B37/042 ,  H01L21/31144 ,  H01L21/76834 ,  H01L21/7684 ,  H01L21/76849 ,  H01L21/76852 ,  H01L21/76885 ,  Y10T29/49156 ,  Y10T29/49165 ,  Y10T29/49204

摘要： Disclosed are a damascene and dual damascene processes both of which incorporate the use of a release layer to remove trace amounts of residual material between metal interconnect lines. The release layer is deposited onto a dielectric layer. The release layer comprises an organic material, a dielectric material, a metal or a metal nitride. Trenches are etched into the dielectric layer. The trenches are lined with a liner and filled with a conductor. The conductor and liner materials are polished off the release layer. However, trace amounts of the residual material may remain. The release layer is removed (e.g., by an appropriate solvent or wet etching process) to remove the residual material. If the trench is formed such that the release layer overlaps the walls of the trench, then when the release layer is removed another dielectric layer can be deposited that reinforces the corners around the top of the metal interconnect line.

摘要翻译： 公开了一种镶嵌和双镶嵌工艺，其中两者都结合使用剥离层以在金属互连线之间移除痕量的残余材料。 释放层沉积在电介质层上。 释放层包括有机材料，电介质材料，金属或金属氮化物。 沟槽蚀刻到电介质层中。 沟槽内衬衬里，填充导体。 导体和衬里材料从剥离层抛光。 然而，痕量的剩余材料可能会残留。 去除脱模层（例如，通过适当的溶剂或湿蚀刻工艺）以除去残留的材料。 如果沟槽形成为使得剥离层与沟槽的壁重叠，则当除去剥离层时，可以沉积另外的介电层，加强围绕金属互连线的顶部的拐角。

公开(公告)号：US20060097394A1

公开(公告)日：2006-05-11

申请号：US10904329

申请日：2004-11-04

申请人： Ronald Filippi ,  Roy Iggulden ,  Edward Kiewra ,  Stephen Loh ,  Ping-Chuan Wang

发明人： Ronald Filippi ,  Roy Iggulden ,  Edward Kiewra ,  Stephen Loh ,  Ping-Chuan Wang

IPC分类号： H01L23/52

CPC分类号： H01L21/7684 ,  H01L21/3212 ,  H01L21/7688 ,  H01L22/24 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method and structure for the detection of residual liner materials after polishing in a damascene processes includes an integrated circuit comprising a substrate; a dielectric layer over the substrate; a marker layer over the dielectric layer; a liner over the marker layer and dielectric layer; and a metal layer over the liner, wherein the marker layer comprises ultraviolet detectable material, which upon excitation by an ultraviolet ray signals an absence of the metal layer and the liner over the marker layer. Moreover, the marker layer comprises a separate layer from the dielectric layer. Additionally, the ultraviolet detectable material comprises fluorescent material or phosphorescent material.

摘要翻译： 用于在镶嵌工艺中抛光之后检测残留衬垫材料的方法和结构包括：包括衬底的集成电路; 介电层; 电介质层上的标记层; 标记层和电介质层上的衬垫; 以及在所述衬里上的金属层，其中所述标记层包括紫外线可检测材料，其在通过紫外线激发时表示在所述标记层上不存在所述金属层和所述衬垫。 此外，标记层包括与电介质层分离的层。 另外，紫外线可检测材料包括荧光材料或磷光材料。

公开(公告)号：US20070115018A1

公开(公告)日：2007-05-24

申请号：US11163948

申请日：2005-11-04

申请人： Kaushik Chanda ,  Birendra Agarwala ,  Lawrence Clevenger ,  Andrew Cowley ,  Ronald Filippi ,  Jason Gill ,  Tom Lee ,  Baozhen Li ,  Paul McLaughlin ,  Du Nguyen ,  Hazara Rathore ,  Timothy Sullivan ,  Chih-Chao Yang

发明人： Kaushik Chanda ,  Birendra Agarwala ,  Lawrence Clevenger ,  Andrew Cowley ,  Ronald Filippi ,  Jason Gill ,  Tom Lee ,  Baozhen Li ,  Paul McLaughlin ,  Du Nguyen ,  Hazara Rathore ,  Timothy Sullivan ,  Chih-Chao Yang

IPC分类号： G01R31/26

CPC分类号： G01R31/2858 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

摘要： A microelectronic element such as a chip or microelectronic wiring substrate is provided which includes a plurality of conductive interconnects for improved resistance to thermal stress. At least some of the conductive interconnects include a metallic plate, a metallic connecting line and an upper metallic via. The metallic connecting line has an upper surface at least substantially level with an upper surface of the metallic plate, an inner end connected to the metallic plate at one of the peripheral edges, and an outer end horizontally displaced from the one peripheral edge. The metallic connecting line has a width much smaller than the width of the one peripheral edge of the metallic plate and has length greater than the width of the one peripheral edge. The upper metallic via has a bottom end in contact with the metallic connecting line at a location that is horizontally displaced from the one peripheral edge by at least about 3 microns (μm).

摘要翻译： 提供了诸如芯片或微电子布线基板的微电子元件，其包括用于改善耐热应力的多个导电互连。 至少一些导电互连件包括金属板，金属连接线和上金属通孔。 所述金属连接线具有与所述金属板的上表面至少基本平齐的上表面，在所述周边边缘中的一个处连接到所述金属板的内端和从所述一个周边边缘水平移位的外端。 金属连接线的宽度远小于金属板的一个周边边缘的宽度，并且其长度大于一个周边边缘的宽度。 上金属通孔在与一个外围边缘水平位移至少约3微米（mum）的位置处具有与金属连接线接触的底端。

公开(公告)号：US20080107149A1

公开(公告)日：2008-05-08

申请号：US12004011

申请日：2007-12-19

申请人： Kaushik Chanda ,  Birendra Agarwala ,  Lawrence Clevenger ,  Andrew Cowley ,  Ronald Filippi ,  Jason Gill ,  Tom Lee ,  Baozhen Li ,  Paul McLaughlin ,  Du Nguyen ,  Hazara Rathore ,  Timothy Sullivan ,  Chih-Chao Yang

发明人： Kaushik Chanda ,  Birendra Agarwala ,  Lawrence Clevenger ,  Andrew Cowley ,  Ronald Filippi ,  Jason Gill ,  Tom Lee ,  Baozhen Li ,  Paul McLaughlin ,  Du Nguyen ,  Hazara Rathore ,  Timothy Sullivan ,  Chih-Chao Yang

IPC分类号： G01N25/72 ,  G01R31/26

CPC分类号： G01R31/2858 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

摘要： A microelectronic element such as a chip or microelectronic wiring substrate is provided which includes a plurality of conductive interconnects for improved resistance to thermal stress. At least some of the conductive interconnects include a metallic plate, a metallic connecting line and an upper metallic via. The metallic connecting line has an upper surface at least substantially level with an upper surface of the metallic plate, an inner end connected to the metallic plate at one of the peripheral edges, and an outer end horizontally displaced from the one peripheral edge. The metallic connecting line has a width much smaller than the width of the one peripheral edge of the metallic plate and has length greater than the width of the one peripheral edge. The upper metallic via has a bottom end in contact with the metallic connecting line at a location that is horizontally displaced from the one peripheral edge by at least about 3 microns (μm).

摘要翻译： 提供了诸如芯片或微电子布线基板的微电子元件，其包括用于改善耐热应力的多个导电互连。 至少一些导电互连件包括金属板，金属连接线和上金属通孔。 所述金属连接线具有与所述金属板的上表面至少基本平齐的上表面，在所述周边边缘中的一个处连接到所述金属板的内端和从所述一个周边边缘水平移位的外端。 金属连接线的宽度远小于金属板的一个周边边缘的宽度，并且其长度大于一个周边边缘的宽度。 上金属通孔在与一个外围边缘水平位移至少约3微米（mum）的位置处具有与金属连接线接触的底端。