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公开(公告)号：US11018253B2
公开(公告)日：2021-05-25
申请号：US14990612
申请日：2016-01-07
Applicant: Lawrence Livermore National Security, LLC
Inventor： Adam Conway , Sara Elizabeth Harrison , Rebecca Nikolic , Qinghui Shao , Lars Voss
IPC: H01L29/78 , H01L29/778 , H01L29/20 , H01L29/205 , H01L29/808 , H01L29/66 , H01L29/06
Abstract: According to one embodiment, an apparatus includes at least one vertical transistor, where the at least one vertical transistor includes: a substrate including a semiconductor material; an array of three dimensional (3D) structures above the substrate; and an isolation region positioned between the 3D structures. Each 3D structure includes the semiconductor material. Each 3D structure also includes a first region having a first conductivity type and a second region having a second conductivity type, where the second region includes a portion of at least one vertical sidewall of the 3D structure.
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公开(公告)号：US12170330B2
公开(公告)日：2024-12-17
申请号：US17238012
申请日：2021-04-22
Applicant: Lawrence Livermore National Security, LLC
Inventor： Adam Conway , Sara Elizabeth Harrison , Rebecca Nikolic , Qinghui Shao , Lars Voss
IPC: H01L29/778 , H01L29/06 , H01L29/20 , H01L29/205 , H01L29/66 , H01L29/78 , H01L29/808
Abstract: An apparatus includes at least one vertical transistor, where the at least one vertical transistor includes: a substrate including a first semiconductor material, an array of three dimensional (3D) structures above the substrate, a sidewall heterojunction layer positioned on at least one vertical sidewall of each 3D structure, and an isolation region positioned between the 3D structures. Each 3D structure includes the first semiconductor material. The sidewall heterojunction layer includes a second semiconductor material, where the first and second semiconductor material have different bandgaps.
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公开(公告)号：US20210159337A1
公开(公告)日：2021-05-27
申请号：US17143972
申请日：2021-01-07
Applicant: Lawrence Livermore National Security, LLC
Inventor： Adam Conway , Sara Elizabeth Harrison , Rebecca Nikolic , Qinghui Shao , Lars Voss
IPC: H01L29/78 , H01L29/778 , H01L29/20 , H01L29/205 , H01L29/808 , H01L29/66 , H01L29/06
Abstract: In one embodiment, an apparatus includes at least one vertical transistor, where the at least one vertical transistor includes: a substrate comprising a semiconductor material, an array of three dimensional (3D) structures above the substrate, a gate region, and an isolation region positioned between the 3D structures. Each 3D structure includes the semiconductor material. Each 3D structure also includes a first region having a first conductivity type and a second region having a second conductivity type, the second region including a portion of at least one vertical sidewall of the 3D structure. The gate region is present on a portion of an upper surface of the second region and the gate region is coupled to a portion of the at least one vertical sidewall of each 3D structure.
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公开(公告)号：US20210328057A1
公开(公告)日：2021-10-21
申请号：US17238012
申请日：2021-04-22
Applicant: Lawrence Livermore National Security, LLC
Inventor： Adam Conway , Sara Elizabeth Harrison , Rebecca Nikolic , Qinghui Shao , Lars Voss
IPC: H01L29/78 , H01L29/778 , H01L29/20 , H01L29/205 , H01L29/808 , H01L29/66 , H01L29/06
Abstract: An apparatus includes at least one vertical transistor, where the at least one vertical transistor includes: a substrate including a first semiconductor material, an array of three dimensional (3D) structures above the substrate, a sidewall heterojunction layer positioned on at least one vertical sidewall of each 3D structure, and an isolation region positioned between the 3D structures. Each 3D structure includes the first semiconductor material. The sidewall heterojunction layer includes a second semiconductor material, where the first and second semiconductor material have different bandgaps.
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公开(公告)号：US20170200820A1
公开(公告)日：2017-07-13
申请号：US14990612
申请日：2016-01-07
Applicant: Lawrence Livermore National Security, LLC
Inventor： Adam Conway , Sara Elizabeth Harrison , Rebecca Nikolic , Qinghui Shao , Lars Voss
IPC: H01L29/778 , H01L29/10 , H01L29/205 , H01L29/66 , H01L29/20
CPC classification number: H01L29/7827 , H01L29/0657 , H01L29/2003 , H01L29/205 , H01L29/66924 , H01L29/7788 , H01L29/7789 , H01L29/8083
Abstract: According to one embodiment, an apparatus includes at least one vertical transistor, where the at least one vertical transistor includes: a substrate including a semiconductor material; an array of three dimensional (3D) structures above the substrate; and an isolation region positioned between the 3D structures. Each 3D structure includes the semiconductor material. Each 3D structure also includes a first region having a first conductivity type and a second region having a second conductivity type, where the second region includes a portion of at least one vertical sidewall of the 3D structure.
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公开(公告)号：US11742424B2
公开(公告)日：2023-08-29
申请号：US17143972
申请日：2021-01-07
Applicant: Lawrence Livermore National Security, LLC
Inventor： Adam Conway , Sara Elizabeth Harrison , Rebecca Nikolic , Qinghui Shao , Lars Voss
IPC: H01L29/772 , H01L29/78 , H01L29/778 , H01L29/20 , H01L29/205 , H01L29/808 , H01L29/66 , H01L29/06
CPC classification number: H01L29/7827 , H01L29/0657 , H01L29/2003 , H01L29/205 , H01L29/66924 , H01L29/7788 , H01L29/7789 , H01L29/8083
Abstract: In one embodiment, an apparatus includes at least one vertical transistor, where the at least one vertical transistor includes: a substrate comprising a semiconductor material, an array of three dimensional (3D) structures above the substrate, a gate region, and an isolation region positioned between the 3D structures. Each 3D structure includes the semiconductor material. Each 3D structure also includes a first region having a first conductivity type and a second region having a second conductivity type, the second region including a portion of at least one vertical sidewall of the 3D structure. The gate region is present on a portion of an upper surface of the second region and the gate region is coupled to a portion of the at least one vertical sidewall of each 3D structure.
