摘要:
A method and apparatus provides the capability for a single function to safely use multiple register windows within the same function, with minimal additional support from the operating system, by specifying a new window pointer, the “Effective Current Window Pointer” (ECWP), to be used in conjunction with the prior art window pointer. According to the present invention, the new window pointer ECWP can be used to override the prior art window pointer in dictating from which register window the operands stipulated by the instructions to be executed are sourced/sinked. Consequently, using the method and apparatus of the invention, the number of spills to memory is reduced, the number of instructions required is decreased, resources are used more efficiently, and costly dependency problems and RAW (read-after-write) stalls are prevented.
摘要:
Improved performance of a chip multithreading (CMT) processor during processing of a cipher is disclosed. The chip multithreading processor may be located on a chip multithreading processor chip that includes a processor cache. The selection of a cipher is received. The cipher is processed by executing a plurality of cryptographic operations on the chip multithreading processor. Lookup tables used during the execution of the plurality of cryptographic operations are determined. The size of at least one of the lookup tables may be increased, such that the at least one lookup table is able to be stored in a processor cache located on the chip multithreading processor chip. Further adjustments may be made to the size of one or more lookup tables depending on the cipher selected, other operations executing on the chip multithreading processor, or both.
摘要:
A computer-implemented method to facilitate administration of a network of members. Members of a network are provided with access to a shared message stream such that the members of the network are able to monitor messages generated by other members of the network posted to the shared message stream, wherein at least some of the messages are indicative of operational conditions of particular other members which generated the messages. Responsive to a first member of the network identifying a specific operational condition of the first member, the shared message stream is monitored for a message related to the specific operational condition. Provided the shared message stream includes a message related to the specific operational condition identified by the first member, an association of the message with an indication that the first member identifies with the specific operational condition is established, wherein the first member is configured to establish the association.
摘要:
A system including a memory; a software interface, operatively connected to the memory, and configured to generate a modified version of a confidentially key (CKey), and a modified version of an integrity key (IKey); and a Kasumi engine having a hardware implementation of a Kasumi cipher and configured to load the modified version of the CKey from the memory to perform a confidentiality function, and to load the modified version of the IKey from memory to perform an integrity function.
摘要:
A method for rapidly mapping a bitmask returned by a Single Instruction Multiple Data (SIMD) computer compare instruction is provided. A user supplied partitioned mapping variable includes multiple mapping elements. Each of the multiple mapping elements is applied to the inputs of a different one of multiple digital multiplexers. The bitmask returned by the SIMD compare instruction is applied to the selects or all of the multiple digital multiplexers. Each multiplexer outputs one bit, as selected by the bitmask, from the respective mapping element applied to each multiplexer. The one bit outputs are accumulated in a mapped output variable as a mapped bitmask.
摘要:
A computer-implemented method for creating a social network of members of a virtualization infrastructure. At a virtualization infrastructure manager, at least a portion of the members of the virtualization infrastructure are identified. Parent/child relationships of identified members of the virtualization infrastructure are identified. A social network of the identified members of the virtualization infrastructure is generated based on the identified parent/child relationships. Affiliation relationships between parent members and child members of the virtualization infrastructure are established, wherein the child members can access shared message streams corresponding to the parent members, such that a child member can establish an association of a message from a shared message stream with an indication that the child member identifies with content of the message.
摘要:
A method of accelerating memory operations using virtualization information includes executing a hypervisor on hardware resources of a computing system. A plurality of domains are created under the control of the hypervisor. Each domain is allocated memory resources that include accessible memory space that is exclusively accessible by that domain. Each domain is allocated one or more processor resources. The hypervisor identifies domain layout information that includes a boundary of accessible memory space of each domain. The hypervisor provides the domain layout information to each processor resource. Each processor resource is configured to implement, on a per domain basis, a restricted coherency protocol based on the domain layout information. The restricted coherency protocol bypasses, relative to the domain, downstream caches when a cache line falls within the accessible memory space of that domain.
摘要:
Techniques are disclosed relating to a processor including instruction support for performing a Montgomery multiplication. The processor may issue, for execution, programmer-selectable instruction from a defined instruction set architecture (ISA). The processor may include an instruction execution unit configured to receive instructions including a first instance of a Montgomery-multiply instruction defined within the ISA. The Montgomery-multiply instruction is executable by the processor to operate on at least operands A, B, and N residing in respective portions of a general-purpose register file of the processor, where at least one of operands A, B, N spans at least two registers of general-purpose register file. The instruction execution unit is configured to calculate P mod N in response to receiving the first instance of the Montgomery-multiply instruction, where P is the product of at least operand A, operand B, and R^−1.
摘要翻译:公开了涉及包括用于执行蒙哥马利乘法的指令支持的处理器的技术。 处理器可以从定义的指令集架构(ISA)发出执行编程器可选择的指令。 处理器可以包括指令执行单元,其被配置为接收包括在ISA内定义的蒙哥马利乘法指令的第一实例的指令。 蒙哥马利乘法指令可由处理器执行,以至少驻留在处理器的通用寄存器文件的相应部分中的操作数A,B和N操作,其中操作数A,B,N中的至少一个跨越 最少两个通用寄存器寄存器。 指令执行单元被配置为响应于接收到蒙哥马利乘法指令的第一实例来计算P mod N,其中P是至少操作数A,操作数B和R ^ -1的乘积。
摘要:
In response to executing an arithmetic instruction, a first number is multiplied by a second number, and a partial result from a previously executed single arithmetic instruction is fed back from a first carry save adder structure generating high order bits of the current arithmetic instruction to a second carry save adder tree structure being utilized to generate low order bits of the current arithmetic instruction to generate a result that represents the first number multiplied by the second number summed with the high order bits from the previously executed arithmetic instruction. Execution of the arithmetic instruction may instead generate a result that represents the first number multiplied by the second number summed with the partial result and also summed with a third number, the third number being fed to the carry save adder tree structure.
摘要:
In response to executing a single arithmetic instruction, a first number is multiplied by a second number, and a partial result from a previously executed single arithmetic instruction is added implicitly to generate a result that represents the first number multiplied by the second number summed with the partial result from a previously executed single arithmetic instruction. The high order portion of the generated result is saved in an extended carry register as a next partial result for use with execution of a subsequent single arithmetic instruction. Execution of a single arithmetic instruction may instead generate a result that represents the first number multiplied by the second number summed with the partial result and also summed with a third number.