利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

661 条记录 (耗时 0.03 秒)

    TAP test clock control circuitry connected to device address port
    1.
    发明授权
    TAP test clock control circuitry connected to device address port 有权
    TAP测试时钟控制电路连接到设备地址端口

    公开(公告)号：US09046575B2

    公开(公告)日：2015-06-02

    申请号：US13596889

    申请日：2012-08-28

    申请人： Lee D. Whetsel

    发明人： Lee D. Whetsel

    IPC分类号： G01R31/3185

    CPC分类号： G01R31/3177 ,  G01R31/31723 ,  G01R31/31727 ,  G01R31/318555 ,  G01R31/318572

    摘要： The disclosure describes a novel method and apparatus for making device TAPs addressable to allow device TAPs to be accessed in a parallel arrangement without the need for having a unique TMS signal for each device TAP in the arrangement. According to the disclosure, device TAPs are addressed by inputting an address on the TDI input of devices on the falling edge of TCK. An address circuit within the device is associated with the device's TAP and responds to the address input to either enable or disable access of the device's TAP.

    摘要翻译： 本公开描述了一种用于使设备TAP可寻址以允许以并行布置访问设备TAP的新颖的方法和装置，而不需要在该布置中为每个设备TAP具有唯一的TMS信号。 根据本公开，通过在TCK的下降沿的设备的TDI输入上输入地址来寻址设备TAP。 设备内的地址电路与设备的TAP相关联，并响应地址输入以启用或禁用设备的TAP访问。

    JTAG shadow protocol circuit with detection, command and address circuits
    2.
    发明授权
    JTAG shadow protocol circuit with detection, command and address circuits 有权
    JTAG阴影协议电路具有检测，命令和地址电路

    公开(公告)号：US08839060B2

    公开(公告)日：2014-09-16

    申请号：US13488956

    申请日：2012-06-05

    申请人： Lee D. Whetsel

    发明人： Lee D. Whetsel

    IPC分类号： G01R31/28 ,  G01R31/3185 ,  G01R31/302

    CPC分类号： G01R31/31713 ,  G01R31/2815 ,  G01R31/2851 ,  G01R31/2884 ,  G01R31/3025 ,  G01R31/31703 ,  G01R31/31725 ,  G01R31/31727 ,  G01R31/3177 ,  G01R31/318558

    摘要： The disclosure describes a process and apparatus for accessing devices on a substrate. The substrate may include only full pin JTAG devices (504), only reduced pin JTAG devices (506), or a mixture of both full pin and reduced pin JTAG devices. The access is accomplished using a single interface (502) between the substrate (408) and a JTAG controller (404). The access interface may be a wired interface or a wireless interface and may be used for JTAG based device testing, debugging, programming, or other type of JTAG based operation.

    摘要翻译： 本公开描述了用于访问基板上的设备的过程和设备。 衬底可以仅包括全引脚JTAG器件（504），只有减少的引脚JTAG器件（506），或者是完全引脚和降低引脚JTAG器件的混合。 使用在基板（408）和JTAG控制器（404）之间的单个接口（502）来实现访问。 访问接口可以是有线接口或无线接口，并且可以用于基于JTAG的设备测试，调试，编程或其他类型的基于JTAG的操作。

    Circuits with selectable paths of control and data scan cells
    3.
    发明授权
    Circuits with selectable paths of control and data scan cells 有权
    具有可选路径控制和数据扫描单元的电路

    公开(公告)号：US08539291B2

    公开(公告)日：2013-09-17

    申请号：US13757334

    申请日：2013-02-01

    申请人： Lee D. Whetsel

    发明人： Lee D. Whetsel

    IPC分类号： G01R31/28

    CPC分类号： G01R31/3177 ,  G01R31/318536

    摘要： An integrated circuit or circuit board includes functional circuitry and a scan path. The scan path includes a test data input lead, a test data output lead, a multiplexer, and scan cells. A dedicated scan cell has a functional data output separate from a test data output. Shared scan cells each have a combined output for functional data and test data. The shared scan cells are coupled in series. The test data input of the first shared scan cell is connected to the test data output of the dedicated scan cell. The combined output of one shared scan cell is coupled to the test data input lead of another shared scan cell. The multiplexer has an input coupled to the test data output, an input connected to the combined output lead of the last shared scan cell in the series, and an output connected in the scan path.

    摘要翻译： 集成电路或电路板包括功能电路和扫描路径。 扫描路径包括测试数据输入引线，测试数据输出引线，多路复用器和扫描单元。 专用扫描单元具有与测试数据输出分开的功能数据输出。 共享扫描单元每个都具有用于功能数据和测试数据的组合输出。 共享扫描单元串联耦合。 第一共享扫描单元的测试数据输入连接到专用扫描单元的测试数据输出。 一个共享扫描单元的组合输出耦合到另一个共享扫描单元的测试数据输入引线。 复用器具有耦合到测试数据输出的输入，连接到串联中的最后共享扫描单元的组合输出引线的输入端和连接在扫描路径中的输出。

    Tap with address, state monitor and gating circuitry
    4.
    发明授权
    Tap with address, state monitor and gating circuitry 有权
    点击地址，状态监视器和门控电路

    公开(公告)号：US08522095B2

    公开(公告)日：2013-08-27

    申请号：US13614615

    申请日：2012-09-13

    申请人： Lee D. Whetsel

    发明人： Lee D. Whetsel

    IPC分类号： G01R31/28

    CPC分类号： G01R31/31724 ,  G01R31/31723 ,  G01R31/31727 ,  G01R31/3177 ,  G01R31/318555 ,  G01R31/318572

    摘要： The disclosure provides a novel method and apparatus for inputting addresses to devices to select the device TAP for access. Further, the disclosure provides a novel method and apparatus for inputting addresses for selecting device TAPs and for inputting commands for commanding circuitry within the device. The inputting of addresses or the inputting of addresses and commands is initiated by a control bit input on TDI that is recognized during the Run Test/Idle, Pause-DR or Pause-IR TAP states.

    摘要翻译： 本公开提供了一种用于向设备输入地址以选择用于访问的设备TAP的新颖的方法和装置。 此外，本公开提供了一种用于输入用于选择设备TAP的地址和用于输入设备内的命令电路的命令的新颖的方法和装置。 输入地址或输入地址和命令由在TDI上输入的控制位启动，在运行测试/空闲，暂停DR或暂停IR TAP状态期间被识别。

    Master reset and synchronizer circuit with data and clock inputs
    6.
    发明授权
    Master reset and synchronizer circuit with data and clock inputs 有权
    主复位和同步电路具有数据和时钟输入

    公开(公告)号：US08433962B2

    公开(公告)日：2013-04-30

    申请号：US13551167

    申请日：2012-07-17

    申请人： Lee D. Whetsel

    发明人： Lee D. Whetsel

    IPC分类号： G01R31/28

    CPC分类号： G01R31/3177 ,  G01R31/2815 ,  G01R31/3172 ,  G01R31/31723 ,  G01R31/31724 ,  G01R31/31727 ,  G01R31/318541 ,  G01R31/318555 ,  G01R31/318558 ,  G01R31/318572 ,  G06F11/3656

    摘要： An optimized JTAG interface is used to access JTAG Tap Domains within an integrated circuit. The interface requires fewer pins than the conventional JTAG interface and is thus more applicable than conventional JTAG interfaces on an integrated circuit where the availability of pins is limited. The interface may be used for a variety of serial communication operations such as, but not limited to, serial communication related integrated circuit test, emulation, debug, and/or trace operations.

    摘要翻译： 优化的JTAG接口用于访问集成电路中的JTAG Tap Domains。 该接口需要比传统JTAG接口更少的引脚，因此比在引脚可用性有限的集成电路上的传统JTAG接口更为适用。 该接口可以用于各种串行通信操作，例如但不限于与串行通信相关的集成电路测试，仿真，调试和/或跟踪操作。

    Taps and hierarchical TLM with shift register, and state machine
    8.
    发明授权
    Taps and hierarchical TLM with shift register, and state machine 有权
    带移位寄存器和状态机的抽头和分级TLM

    公开(公告)号：US08356219B2

    公开(公告)日：2013-01-15

    申请号：US13464477

    申请日：2012-05-04

    申请人： Lee D. Whetsel

    发明人： Lee D. Whetsel

    IPC分类号： G01R31/28

    CPC分类号： G01R31/3177 ,  G01R31/318555 ,  G01R31/318558 ,  G01R31/318561 ,  G01R31/318563 ,  G01R31/318572

    摘要： An integrated circuit can have plural core circuits, each having a test access port that is defined in IEEE standard 1149.1. Access to and control of these ports is though a test linking module. The test access ports on an integrated circuit can be arranged in a hierarchy with one test linking module controlling access to plural secondary test linking modules and test access ports. Each secondary test linking module in turn can also control access to tertiary test linking modules and test access ports. The test linking modules can also be used for emulation.

    摘要翻译： 集成电路可以具有多个核心电路，每个核心电路具有在IEEE标准1149.1中定义的测试访问端口。 这些端口的访问和控制是一个测试链接模块。 集成电路上的测试访问端口可以以一个测试链接模块来控制对多个辅助测试链接模块和测试访问端口的访问的层次结构。 每个次级测试链接模块又可以控制对三级测试链接模块和测试访问端口的访问。 测试链接模块也可用于仿真。

    Multiplexer input linking circuitry to IC and core TAP domains
    10.
    发明授权
    Multiplexer input linking circuitry to IC and core TAP domains 有权
    多路复用器输入链路电路到IC和核心TAP域

    公开(公告)号：US08332700B2

    公开(公告)日：2012-12-11

    申请号：US13330178

    申请日：2011-12-19

    申请人： Lee D. Whetsel ,  Baher S. Haroun ,  Brian J. Lasher ,  Anjali Kinra

    发明人： Lee D. Whetsel ,  Baher S. Haroun ,  Brian J. Lasher ,  Anjali Kinra

    IPC分类号： G01R31/28

    CPC分类号： G01R31/3177 ,  G01R31/31727 ,  G01R31/318555

    摘要： IEEE 1149.1 Test Access Ports (TAPs) may be utilized at both IC and intellectual property core design levels. TAPs serve as serial communication ports for accessing a variety of embedded circuitry within ICs and cores including; IEEE 1149.1 boundary scan circuitry, built in test circuitry, internal scan circuitry, IEEE 1149.4 mixed signal test circuitry, IEEE P5001 in-circuit emulation circuitry, and IEEE P1532 in-system programming circuitry. Selectable access to TAPs within ICs is desirable since in many instances being able to access only the desired TAP(s) leads to improvements in the way testing, emulation, and programming may be performed within an IC. A TAP linking module is described that allows TAPs embedded within an IC to be selectively accessed using 1149.1 instruction scan operations.

    摘要翻译： IEEE 1149.1测试接入端口（TAP）可用于IC和知识产权核心设计级别。 TAP用作用于访问IC和核心内的各种嵌入式电路的串行通信端口，包括： IEEE 1149.1边界扫描电路，内置测试电路，内部扫描电路，IEEE 1149.4混合信号测试电路，IEEE P5001在线仿真电路和IEEE P1532系统编程电路。 可选择地访问IC内的TAP是理想的，因为在许多情况下，仅能够访问期望的TAP导致在IC内可以执行测试，仿真和编程的方式的改进。 描述了一种TAP链接模块，其允许使用1149.1指令扫描操作来选择性地访问嵌入在IC内的TAP。