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公开(公告)号:US08809936B2
公开(公告)日:2014-08-19
申请号:US11461428
申请日:2006-07-31
申请人: Lei Xue , Rinji Sugino , YouSeok Suh , Hidehiko Shiraiwa , Meng Ding , Shenqing Fang , Joong Jeon
发明人: Lei Xue , Rinji Sugino , YouSeok Suh , Hidehiko Shiraiwa , Meng Ding , Shenqing Fang , Joong Jeon
IPC分类号: H01L29/788
CPC分类号: H01L21/28282 , H01L27/115 , H01L27/11568 , H01L29/4234 , H01L29/513
摘要: A memory cell system is provided including forming a first insulator layer over a semiconductor substrate, forming a charge trap layer over the first insulator layer, forming a second insulator layer over the charge trap layer, forming a top blocking intermediate layer over the second insulator layer, and forming a contact layer over the top blocking intermediate layer.
摘要翻译: 提供一种存储单元系统,包括在半导体衬底上形成第一绝缘体层,在第一绝缘体层上形成电荷陷阱层,在电荷陷阱层上形成第二绝缘体层,在第二绝缘体层上形成顶部阻挡中间层 并且在顶部阻挡中间层上形成接触层。
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公开(公告)号:US20080023750A1
公开(公告)日:2008-01-31
申请号:US11461428
申请日:2006-07-31
申请人: Lei Xue , Rinji Sugino , YouSeok Suh , Hidehiko Shiraiwa , Meng Ding , Shenqing Fang , Joong Jeon
发明人: Lei Xue , Rinji Sugino , YouSeok Suh , Hidehiko Shiraiwa , Meng Ding , Shenqing Fang , Joong Jeon
IPC分类号: H01L29/788
CPC分类号: H01L21/28282 , H01L27/115 , H01L27/11568 , H01L29/4234 , H01L29/513
摘要: A memory cell system is provided including forming a first insulator layer over a semiconductor substrate, forming a charge trap layer over the first insulator layer, forming a second insulator layer over the charge trap layer, forming a top blocking intermediate layer over the second insulator layer, and forming a contact layer over the top blocking intermediate layer.
摘要翻译: 提供一种存储单元系统,包括在半导体衬底上形成第一绝缘体层,在第一绝缘体层上形成电荷陷阱层,在电荷陷阱层上形成第二绝缘体层,在第二绝缘体层上形成顶部阻挡中间层 并且在顶部阻挡中间层上形成接触层。
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公开(公告)号:US20080083946A1
公开(公告)日:2008-04-10
申请号:US11539984
申请日:2006-10-10
申请人: Shenqing Fang , Rinji Sugino , Jayendra Bhakta , Takashi Orimoto , Hiroyuki Nansei , Yukio Hayakawa , Takayuki Maruyama , Hidehiko Shiraiwa , Kuo-Tung Chang , Lei Xue , Meng Ding , Amol Ramesh Joshi , YouSeok Suh , Harpreet Sachar
发明人: Shenqing Fang , Rinji Sugino , Jayendra Bhakta , Takashi Orimoto , Hiroyuki Nansei , Yukio Hayakawa , Takayuki Maruyama , Hidehiko Shiraiwa , Kuo-Tung Chang , Lei Xue , Meng Ding , Amol Ramesh Joshi , YouSeok Suh , Harpreet Sachar
IPC分类号: H01L29/792 , H01L21/8238
CPC分类号: H01L29/792 , H01L21/28273 , H01L27/115 , H01L27/11568
摘要: A memory cell system is provided including forming a first insulator layer over a semiconductor substrate, forming a charge trap layer over the first insulator layer, and slot plane antenna plasma oxidizing the charge trap layer for forming a second insulator layer.
摘要翻译: 提供了一种存储单元系统,包括在半导体衬底上形成第一绝缘体层,在第一绝缘体层上形成电荷陷阱层,以及缝隙平面天线等离子体氧化用于形成第二绝缘体层的电荷陷阱层。
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公开(公告)号:US08143661B2
公开(公告)日:2012-03-27
申请号:US11539984
申请日:2006-10-10
申请人: Shenqing Fang , Rinji Sugino , Jayendra Bhakta , Takashi Orimoto , Hiroyuki Nansei , Yukio Hayakawa , Takayuki Maruyama , Hidehiko Shiraiwa , Kuo-Tung Chang , Lei Xue , Meng Ding , Amol Ramesh Joshi , YouSeok Suh , Harpreet Sachar
发明人: Shenqing Fang , Rinji Sugino , Jayendra Bhakta , Takashi Orimoto , Hiroyuki Nansei , Yukio Hayakawa , Takayuki Maruyama , Hidehiko Shiraiwa , Kuo-Tung Chang , Lei Xue , Meng Ding , Amol Ramesh Joshi , YouSeok Suh , Harpreet Sachar
IPC分类号: H01L29/792
CPC分类号: H01L29/792 , H01L21/28273 , H01L27/115 , H01L27/11568
摘要: A memory cell system is provided including a first insulator layer over a semiconductor substrate, a charge trap layer over the first insulator layer, and slot where the charge trap layer includes a second insulator layer having the characteristic of being grown.
摘要翻译: 提供一种存储单元系统,包括半导体衬底上的第一绝缘体层,第一绝缘体层上的电荷陷阱层和电荷陷阱层包括具有生长特性的第二绝缘体层的槽。
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公开(公告)号:US20080150011A1
公开(公告)日:2008-06-26
申请号:US11958646
申请日:2007-12-18
申请人: Simon Siu-Sing Chan , Lei Xue , YouSeok Suh , Amol Ramesh Joshi , Hidehiko Shiraiwa , Harpreet Sachar , Kuo-Tung Chang , Connie Pin Chin Wang , Paul R. Besser , Shenqing Fang , Meng Ding , Takashi Orimoto , Wei Zheng , Fred TK Cheung
发明人: Simon Siu-Sing Chan , Lei Xue , YouSeok Suh , Amol Ramesh Joshi , Hidehiko Shiraiwa , Harpreet Sachar , Kuo-Tung Chang , Connie Pin Chin Wang , Paul R. Besser , Shenqing Fang , Meng Ding , Takashi Orimoto , Wei Zheng , Fred TK Cheung
IPC分类号: H01L27/115 , H01L21/8247
CPC分类号: H01L27/11568 , H01L27/105 , H01L27/11573
摘要: A method for forming an integrated circuit system is provided including forming a substrate having a core region and a periphery region, forming a charge storage stack over the substrate in the core region, forming a gate stack with a stack header having a metal portion over the substrate in the periphery region, and forming a memory system with the stack header over the charge storage stack.
摘要翻译: 提供一种用于形成集成电路系统的方法,包括形成具有芯区域和周边区域的衬底,在芯区域中的衬底上形成电荷存储堆叠,形成具有堆叠集管的栅极堆叠,堆叠集束具有金属部分 衬底,并且在电荷存储堆叠上形成具有堆叠头的存储器系统。
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公开(公告)号:US20080150000A1
公开(公告)日:2008-06-26
申请号:US11614839
申请日:2006-12-21
申请人: YouSeok Suh , Hidehiko Shiraiwa , Kuo-Tung Chang , Lei Xue , Meng Ding , Amol Ramesh Joshi , Shenqing Fang
发明人: YouSeok Suh , Hidehiko Shiraiwa , Kuo-Tung Chang , Lei Xue , Meng Ding , Amol Ramesh Joshi , Shenqing Fang
IPC分类号: H01L29/792 , H01L21/28
CPC分类号: H01L29/792 , H01L29/40117
摘要: A memory system includes a substrate, forming a first insulator over the substrate, forming a charge trap layer, having a composition for setting a predetermined electrical charge level, over the first insulator, and forming a second insulator over the charge trap layer.
摘要翻译: 存储器系统包括:衬底,在衬底上形成第一绝缘体,在第一绝缘体上形成具有用于设定预定电荷水平的组成的电荷陷阱层,以及在电荷陷阱层上形成第二绝缘体。
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公开(公告)号:US07416940B1
公开(公告)日:2008-08-26
申请号:US11418352
申请日:2006-05-03
申请人: Satoshi Torii , Hidehiko Shiraiwa , Youseok Suh , Lei Xue
发明人: Satoshi Torii , Hidehiko Shiraiwa , Youseok Suh , Lei Xue
IPC分类号: H01L21/336
CPC分类号: H01L27/115 , H01L27/11568
摘要: Methods for fabricating a flash memory device are provided. A method comprises forming a plurality of gate stacks overlying a substrate. Each gate stack comprises a charge trapping layer and a control gate. The control gate is a first distance from the substrate. Adjacent gate stacks are a second distance apart. A cell spacer material layer is deposited and is etched to form a spacer about sidewalls of each gate stack. A source/drain impurity doped region is formed adjacent a first gate stack and a last gate stack. The first distance and the second distance are such that, when a voltage is applied to a gate stack during a READ operation, a fringing field is created between the control gate of the gate stack and the substrate and is sufficient to invert a portion of the substrate between the gate stack and an adjacent gate stack.
摘要翻译: 提供了制造闪速存储器件的方法。 一种方法包括形成覆盖衬底的多个栅叠层。 每个栅极堆叠包括电荷捕获层和控制栅极。 控制栅极是离基板的第一距离。 相邻的门堆叠是第二个距离。 沉积电池间隔物材料层并被蚀刻以形成围绕每个栅极叠层的侧壁的间隔物。 在第一栅极堆叠和最后一个栅极堆叠附近形成源极/漏极杂质掺杂区域。 第一距离和第二距离使得当在读取操作期间将电压施加到栅极堆叠时,在栅极堆叠的控制栅极和衬底之间产生边缘场,并且足以将一部分 栅极堆叠和相邻栅极堆叠之间的衬底。
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公开(公告)号:US08809206B2
公开(公告)日:2014-08-19
申请号:US13022517
申请日:2011-02-07
申请人: Rinji Sugino , Bradley Marc Davis , Lei Xue , Kenichi Ohtsuka
发明人: Rinji Sugino , Bradley Marc Davis , Lei Xue , Kenichi Ohtsuka
IPC分类号: H01L21/31
CPC分类号: H01L21/02271 , C23C16/045 , C23C16/44 , C23C16/56 , H01L21/02164 , H01L27/11568
摘要: A method for semiconductor device fabrication is provided. The present invention is directed towards using at least one patterned dummy wafer along with one or more product wafers in a film deposition system to create a sidewall layer thickness variation that is substantially uniform across all product wafers. The at least one patterned dummy wafer may have a high density patterned substrate surface with a topography that is different from or substantially similar to a topography of the one or more product wafers. Furthermore, in a batch type Chemical Vapor Deposition (CVD) system, the at least one patterned dummy wafer may be placed near a gas inlet of the CVD system. At least one patterned dummy wafer may be placed near an exhaust of the CVD system. Additionally, the patterned dummy wafers may be reusable in subsequent film deposition processes.
摘要翻译: 提供了半导体器件制造方法。 本发明涉及在膜沉积系统中使用至少一个图案化虚设晶圆以及一个或多个产品晶片,以产生在所有产品晶片上基本均匀的侧壁层厚度变化。 至少一个图案化的虚设晶片可以具有高密度图案化的衬底表面,其具有不同于或基本类似于一个或多个产品晶片的形貌的形貌。 此外,在间歇式化学气相沉积(CVD)系统中,至少一个图案化的虚设晶片可以放置在CVD系统的气体入口附近。 至少一个图案化的虚设晶片可以放置在CVD系统的排气附近。 此外,图案化的虚拟晶片可以在随后的成膜工艺中可重复使用。
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公开(公告)号:US20120202355A1
公开(公告)日:2012-08-09
申请号:US13022517
申请日:2011-02-07
申请人: Rinji Sugino , Bradley Marc Davis , Lei Xue , Kenichi Ohtsuka
发明人: Rinji Sugino , Bradley Marc Davis , Lei Xue , Kenichi Ohtsuka
IPC分类号: H01L21/465 , H01L21/46
CPC分类号: H01L21/02271 , C23C16/045 , C23C16/44 , C23C16/56 , H01L21/02164 , H01L27/11568
摘要: A method for semiconductor device fabrication is provided. Embodiments of the present invention are directed towards using at least one patterned dummy wafer along with one or more product wafers in a film deposition system to create a sidewall layer thickness variation that is substantially uniform across all product wafers. The at least one patterned dummy wafer may have a high density patterned substrate surface with a topography that is different from or substantially similar to a topography of the one or more product wafers. Furthermore, in a batch type Chemical Vapor Deposition (CVD) system, the at least one patterned dummy wafer may be placed near a gas inlet of the CVD system. In another embodiment, at least one patterned dummy wafer may be placed near an exhaust of the CVD system. Additionally, the patterned dummy wafers may be reusable in subsequent film deposition processes.
摘要翻译: 提供了半导体器件制造方法。 本发明的实施例涉及在膜沉积系统中使用至少一个图案化虚设晶圆以及一个或多个产品晶片,以产生在所有产品晶片上基本均匀的侧壁层厚度变化。 至少一个图案化的虚设晶片可以具有高密度图案化的衬底表面,其具有不同于或基本类似于一个或多个产品晶片的形貌的形貌。 此外,在间歇式化学气相沉积(CVD)系统中,至少一个图案化的虚设晶片可以放置在CVD系统的气体入口附近。 在另一个实施例中,至少一个图案化虚设晶片可以放置在CVD系统的排气附近。 此外,图案化的虚拟晶片可以在随后的成膜工艺中可重复使用。
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公开(公告)号:US20080191269A1
公开(公告)日:2008-08-14
申请号:US11997464
申请日:2006-07-21
申请人: Youseok Suh , Satoshi Torii , Lei Xue
发明人: Youseok Suh , Satoshi Torii , Lei Xue
IPC分类号: H01L29/792
CPC分类号: H01L29/7881 , H01L21/28282 , H01L29/42324 , H01L29/513 , H01L29/792
摘要: A memory device (100) may include a substrate (110), a dielectric layer (210) formed on the substrate (110) and a charge storage element (220) formed on the dielectric layer (210). The memory device (100) may also include an inter-gate dielectric (230) formed on the charge storage element (220), a barrier layer (240) formed on the inter-gate dielectric (230) and a control gate (250) formed on the barrier layer (240). The barrier layer (240) prevents reaction between the control gate (250) and the inter-gate dielectric (230).
摘要翻译: 存储器件(100)可以包括衬底(110),形成在衬底(110)上的电介质层(210)和形成在电介质层(210)上的电荷存储元件(220)。 存储器件(100)还可以包括形成在电荷存储元件(220)上的栅极间电介质(230),形成在栅极间电介质(230)上的阻挡层(240)和控制栅极(250) 形成在阻挡层(240)上。 阻挡层(240)防止控制栅极(250)和栅极间电介质(230)之间的反应。
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