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    CONFINED SPACERS FOR DOUBLE GATE TRANSISTOR SEMICONDUCTOR FABRICATION PROCESS
    1.
    发明申请
    CONFINED SPACERS FOR DOUBLE GATE TRANSISTOR SEMICONDUCTOR FABRICATION PROCESS 有权
    双栅极晶体管半导体制造工艺的限制间隔

    公开(公告)号：US20050101069A1

    公开(公告)日：2005-05-12

    申请号：US10695163

    申请日：2003-10-28

    申请人： Leo Mathew ,  Rode Mora ,  Bich-Yen Nguyen ,  Tab Stephens ,  Anne Vandooren

    发明人： Leo Mathew ,  Rode Mora ,  Bich-Yen Nguyen ,  Tab Stephens ,  Anne Vandooren

    IPC分类号： H01L21/336 ,  H01L21/8234 ,  H01L29/423 ,  H01L29/49 ,  H01L29/786 ,  H01L21/00 ,  H01L21/8238 ,  H01L21/84

    CPC分类号： H01L29/785 ,  H01L21/823437 ,  H01L21/823468 ,  H01L29/66628 ,  H01L29/66795 ,  H01L29/66818

    摘要： A semiconductor fabrication process includes forming a silicon fin overlying a substrate. A gate dielectric is formed on primary faces of the fin. A gate electrode is formed over at least two faces of the fin. Dielectric spacers are then selectively formed in close proximity and confined to the sidewalls of the gate electrode thereby leaving a majority of the primary fin faces exposed. Thereafter a silicide is formed on the primary fin faces. The forming of the gate electrode in one embodiment includes depositing polysilicon over the fin and substrate, depositing a capping layer over the polysilicon, patterning photoresist over the capping layer and etching through the capping layer and the polysilicon with the patterned photoresist in place wherein the etching produces a polysilicon width that is less than a width of the capping layer to create voids under the capping layer adjacent sidewalls of the polysilicon where the confined spacers can be formed.

    摘要翻译： 半导体制造工艺包括形成覆盖衬底的硅片。 栅极电介质形成在鳍片的主面上。 在鳍片的至少两个面上形成栅电极。 然后选择性地形成电介质间隔物并且限制在栅电极的侧壁，从而使大部分初级鳍片面露出。 此后，在主翅片面上形成硅化物。 在一个实施例中，栅电极的形成包括在鳍片和衬底上沉积多晶硅，在多晶硅上沉积覆盖层，在覆盖层上图案化光刻胶，并通过覆盖层和多晶硅蚀刻图案化的光致抗蚀剂，其中蚀刻 产生小于封盖层的宽度的多晶硅宽度，以在与可以形成约束间隔物的多晶硅侧壁相邻的封盖层下产生空隙。

    Multiple gate transistor employing monocrystalline silicon walls
    2.
    发明授权
    Multiple gate transistor employing monocrystalline silicon walls 有权
    采用单晶硅壁的多栅极晶体管

    公开(公告)号：US06753216B2

    公开(公告)日：2004-06-22

    申请号：US10285059

    申请日：2002-10-31

    申请人： Leo Mathew ,  Bich-Yen Nguyen ,  Daniel Thanh-Khac Pham ,  Anne Vandooren

    发明人： Leo Mathew ,  Bich-Yen Nguyen ,  Daniel Thanh-Khac Pham ,  Anne Vandooren

    IPC分类号： H01L218238

    CPC分类号： H01L29/785 ,  H01L29/42384 ,  H01L29/66795 ,  H01L29/78603 ,  H01L29/78621

    摘要： A semiconductor fabrication process and structure in which a dielectric structure (106) is formed upon a substrate (102). Silicon is then deposited and processed to form a crystalline silicon wall (118) that envelopes the dielectric structure (106) and is physically and electrically isolated from the substrate (102). A gate dielectric film (130) is formed over at least two surfaces of the silicon wall (118) and a gate electrode film (132) is formed over the gate dielectric (130). The gate electrode film (132) is then patterned followed by conventional source/drain implant processing. Portions of the silicon wall (118) disposed on either side of the gate electrode (140) may then be contacted to form source/drain structures (150). In this manner, the portion of the silicon wall (118) covered by the gate electrode (140) comprises a transistor channel region having multiple surfaces controlled by gate electrode (140).

    摘要翻译： 一种在衬底（102）上形成电介质结构（106）的半导体制造工艺和结构。 然后沉积和处理硅以形成包封电介质结构（106）并与衬底（102）物理和电气隔离的晶体硅壁（118）。 在硅壁（118）的至少两个表面上形成栅极电介质膜（130），并且在栅极电介质（130）上形成栅电极膜（132）。 然后对栅极电极膜（132）进行构图，然后进行常规的源极/漏极注入处理。 设置在栅电极（140）的任一侧的硅壁（118）的部分然后可以接触以形成源极/漏极结构（150）。 以这种方式，由栅电极（140）覆盖的硅壁（118）的部分包括具有由栅电极（140）控制的多个表面的晶体管沟道区。