公开(公告)号：US20050101069A1

公开(公告)日：2005-05-12

申请号：US10695163

申请日：2003-10-28

申请人： Leo Mathew ,  Rode Mora ,  Bich-Yen Nguyen ,  Tab Stephens ,  Anne Vandooren

发明人： Leo Mathew ,  Rode Mora ,  Bich-Yen Nguyen ,  Tab Stephens ,  Anne Vandooren

IPC分类号： H01L21/336 ,  H01L21/8234 ,  H01L29/423 ,  H01L29/49 ,  H01L29/786 ,  H01L21/00 ,  H01L21/8238 ,  H01L21/84

CPC分类号： H01L29/785 ,  H01L21/823437 ,  H01L21/823468 ,  H01L29/66628 ,  H01L29/66795 ,  H01L29/66818

摘要： A semiconductor fabrication process includes forming a silicon fin overlying a substrate. A gate dielectric is formed on primary faces of the fin. A gate electrode is formed over at least two faces of the fin. Dielectric spacers are then selectively formed in close proximity and confined to the sidewalls of the gate electrode thereby leaving a majority of the primary fin faces exposed. Thereafter a silicide is formed on the primary fin faces. The forming of the gate electrode in one embodiment includes depositing polysilicon over the fin and substrate, depositing a capping layer over the polysilicon, patterning photoresist over the capping layer and etching through the capping layer and the polysilicon with the patterned photoresist in place wherein the etching produces a polysilicon width that is less than a width of the capping layer to create voids under the capping layer adjacent sidewalls of the polysilicon where the confined spacers can be formed.

摘要翻译： 半导体制造工艺包括形成覆盖衬底的硅片。 栅极电介质形成在鳍片的主面上。 在鳍片的至少两个面上形成栅电极。 然后选择性地形成电介质间隔物并且限制在栅电极的侧壁，从而使大部分初级鳍片面露出。 此后，在主翅片面上形成硅化物。 在一个实施例中，栅电极的形成包括在鳍片和衬底上沉积多晶硅，在多晶硅上沉积覆盖层，在覆盖层上图案化光刻胶，并通过覆盖层和多晶硅蚀刻图案化的光致抗蚀剂，其中蚀刻 产生小于封盖层的宽度的多晶硅宽度，以在与可以形成约束间隔物的多晶硅侧壁相邻的封盖层下产生空隙。

公开(公告)号：US20070093010A1

公开(公告)日：2007-04-26

申请号：US11257973

申请日：2005-10-25

申请人： Leo Mathew ,  Rode Mora

发明人： Leo Mathew ,  Rode Mora

IPC分类号： H01L21/338

CPC分类号： H01L27/1104 ,  H01L21/823431 ,  H01L27/11 ,  H01L29/66795 ,  H01L29/785

摘要： A method for creating an inverse T field effect transistor is provided. The method includes creating a horizontal active region and a vertical active region on a substrate. The method further comprises forming a sidewall spacer on a first side of the vertical active region and a second side of the vertical active region. The method further includes removing a portion of the horizontal active region, which is not covered by the sidewall spacer. The method further includes removing the sidewall spacer. The method further includes forming a gate dielectric over at least a first part of the horizontal active region and at least a first part of the vertical active region. The method further includes forming a gate electrode over the gate dielectric. The method further includes forming a source region and a drain region over at least a second part of the horizontal active region and at least a second part of the vertical active region.

摘要翻译： 提供了一种用于产生逆T场效应晶体管的方法。 该方法包括在衬底上创建水平有源区和垂直有源区。 该方法还包括在垂直有源区的第一侧和垂直有源区的第二侧上形成侧壁间隔物。 该方法还包括移除未被侧壁间隔物覆盖的水平有源区的一部分。 该方法还包括去除侧壁间隔物。 该方法还包括在水平有源区域的至少第一部分和垂直有源区域的至少第一部分上形成栅极电介质。 该方法还包括在栅极电介质上形成栅电极。 该方法还包括在水平有源区域的至少第二部分和垂直有源区域的至少第二部分上形成源极区域和漏极区域。

公开(公告)号：US20070059911A1

公开(公告)日：2007-03-15

申请号：US11226826

申请日：2005-09-14

申请人： Dharmesh Jawarani ,  John Alvis ,  Michael Harrison ,  Leo Mathew ,  John Moore ,  Rode Mora

发明人： Dharmesh Jawarani ,  John Alvis ,  Michael Harrison ,  Leo Mathew ,  John Moore ,  Rode Mora

IPC分类号： H01L21/3205

CPC分类号： H01L21/28518 ,  H01L21/2855

摘要： A semiconductor fabrication process includes forming a gate electrode (112) overlying a gate dielectric (114) overlying a semiconductor substrate (104) of a wafer (101) and a liner dielectric layer (116) including vertical portions (118) adjacent sidewalls of the gate electrode and horizontal portions (117) overlying an upper surface of the semiconductor substrate (104). A spacer (108) is formed adjacent a vertical portion (118) and overlying a horizontal portion (117) of the liner dielectric layer (116). After forming the spacer (108), exposed portions of the liner dielectric layer (116) are removed to form a liner dielectric structure (126) covered by the extension spacer (108). The extension spacer (108) is then etched back to expose or uncover extremities of the liner dielectric structure (126). Prior to etching back the spacer (108), a metal (130) may be sputtered deposited over the wafer (101) preparatory to forming a silicide (134). After the etch back the wafer (101) may be dipped in piranha solution and cleaned with an RF sputter (140) of argon.

摘要翻译： 半导体制造工艺包括形成覆盖在晶片（101）的半导体衬底（104）上的栅极电介质（114）上的栅电极（112）和包括垂直部分（118）的衬垫电介质层（116） 栅电极和覆盖在半导体衬底（104）的上表面上的水平部分（117）。 邻近垂直部分（118）并且覆盖衬里介电层（116）的水平部分（117）形成间隔物（108）。 在形成间隔物（108）之后，去除衬里电介质层（116）的暴露部分以形成被延伸间隔物（108）覆盖的衬里电介质结构（126）。 然后将延伸垫片（108）回蚀刻以露出或揭开衬垫介质结构（126）的四肢。 在蚀刻回间隔物（108）之前，金属（130）可以溅射沉积在晶片（101）上，准备形成硅化物（134）。 在蚀刻之后，晶片（101）可以浸入食人鱼溶液中并用氩气的RF溅射（140）清洁。

公开(公告)号：US20050250287A1

公开(公告)日：2005-11-10

申请号：US10839385

申请日：2004-05-05

申请人： Jian Chen ,  Rode Mora ,  Marc Rossow ,  Yasuhito Shiho

发明人： Jian Chen ,  Rode Mora ,  Marc Rossow ,  Yasuhito Shiho

IPC分类号： H01L21/265 ,  H01L21/336 ,  H01L29/78

CPC分类号： H01L29/6656 ,  H01L21/26586 ,  H01L29/66492 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66628 ,  H01L29/66772 ,  H01L29/7834

摘要： A semiconductor fabrication process includes forming a gate electrode overlying a substrate. A first silicon nitride spacer is formed adjacent the gate electrode sidewalls and a disposable silicon nitride spacer is then formed adjacent the offset spacer. An elevated source/drain structure, defined by the boundaries of the disposable spacer, is then formed epitaxially. The disposable spacer is then removed to expose the substrate proximal to the gate electrode and a shallow implant, such as a halo or extension implant, is introduced into the exposed substrate proximal the gate electrode. A replacement spacer is formed substantially where the disposable spacer existed a source/drain implant is done to introduce a source/drain impurity distribution into the elevated source drain. The gate electrode may include an overlying silicon nitride capping layer and the first silicon nitride spacer may contact the capping layer to surround the polysilicon gate electrode in silicon nitride.

摘要翻译： 半导体制造工艺包括形成覆盖衬底的栅电极。 在栅电极侧壁附近形成第一氮化硅间隔物，然后在偏移间隔物附近形成一次性氮化硅间隔物。 然后由一次性间隔件的边界限定的升高的源极/漏极结构外延形成。 然后去除一次性间隔件以暴露基板靠近栅电极，并且将浅的植入物（例如晕或延伸植入物）引入靠近栅电极的暴露的基底中。 基本上形成替代间隔物，其中一次性间隔物存在，进行源极/漏极注入以将源极/漏极杂质分布引入升高的源极漏极。 栅电极可以包括上覆的氮化硅覆盖层，并且第一氮化硅间隔物可接触覆盖层以在氮化硅中包围多晶硅栅电极。

公开(公告)号：US20070249127A1

公开(公告)日：2007-10-25

申请号：US11409882

申请日：2006-04-24

申请人： Rode Mora ,  Vance Adams ,  Venkat Kolagunta ,  Michael Turner ,  Toni Van Gompel

发明人： Rode Mora ,  Vance Adams ,  Venkat Kolagunta ,  Michael Turner ,  Toni Van Gompel

IPC分类号： H01L21/336 ,  H01L27/12

CPC分类号： H01L21/84 ,  H01L27/1203

摘要： An electronic device can include a substrate, an insulating layer, and a semiconductor layer overlying the insulating layer, wherein the insulating layer lies between the substrate and the semiconductor layer. In one aspect, a process of forming the electronic device can include patterning the semiconductor layer to define an opening extending to the insulating layer. The semiconductor layer has a sidewall and a surface, the surface is spaced apart from the insulating layer, and the sidewall extends from the surface towards the insulating layer. The process can also include forming a sidewall spacer adjacent to the sidewall, wherein the sidewall spacer lies within the opening and adjacent to the sidewall, and is spaced apart from the surface. In another aspect, the electronic device can include a field isolation region including the sidewall spacer.

摘要翻译： 电子器件可以包括衬底，绝缘层和覆盖绝缘层的半导体层，其中绝缘层位于衬底和半导体层之间。 一方面，形成电子器件的工艺可以包括图案化半导体层以限定延伸到绝缘层的开口。 半导体层具有侧壁和表面，表面与绝缘层间隔开，并且侧壁从表面向绝缘层延伸。 该方法还可以包括形成邻近侧壁的侧壁间隔物，其中侧壁间隔物位于开口内且与侧壁相邻并且与表面间隔开。 在另一方面，电子设备可以包括包括侧壁间隔物的场隔离区域。

公开(公告)号：US20070197011A1

公开(公告)日：2007-08-23

申请号：US11360318

申请日：2006-02-22

申请人： Anadi Srivastava ,  Paul Grudowski ,  Dharmesh Jawarani ,  Rode Mora

发明人： Anadi Srivastava ,  Paul Grudowski ,  Dharmesh Jawarani ,  Rode Mora

IPC分类号： H01L21/4763 ,  H01L21/3205

CPC分类号： H01L21/76895 ,  H01L21/28052 ,  H01L29/665 ,  H01L29/6653

摘要： A method is provided for making a silicided gate (209). In accordance with the method, a semiconductor substrate (202) is provided which has a gate (209) disposed thereon and which has a spacer (219) disposed adjacent to the gate. The spacer is subjected to a recess etch which exposes a lateral portion of the gate. An implant region (215) is then created adjacent to the spacer, and a layer of silicide (225) is formed which extends over the exposed lateral portion of the gate.

摘要翻译： 提供了一种制造硅化栅（209）的方法。 根据该方法，提供一种半导体衬底（202），其具有设置在其上的栅极（209），并且具有邻近栅极设置的间隔物（219）。 间隔件进行凹口蚀刻，露出栅极的侧面部分。 然后在间隔物附近产生注入区域（215），并且形成一层硅化物（225），其在栅极的暴露侧面部分上延伸。

公开(公告)号：US20070178661A1

公开(公告)日：2007-08-02

申请号：US11342102

申请日：2006-01-27

申请人： Toni Gompel ,  John Hackenberg ,  Rode Mora ,  Suresh Venkatesan

发明人： Toni Gompel ,  John Hackenberg ,  Rode Mora ,  Suresh Venkatesan

IPC分类号： H01L21/76

CPC分类号： H01L21/76224 ,  Y10S438/911

摘要： A method for forming a semiconductor isolation trench includes forming a pad oxide layer over a substrate and forming a barrier layer over the substrate. A masking layer is formed over the barrier layer and is patterned to form at least one opening in the masking layer. At least a part of the barrier layer and at least a part of the pad oxide layer are etched through the at least one opening resulting in a trench pad oxide layer. Etching of the trench pad oxide layer stops substantially at a top surface of the substrate within the isolation trench. An oxide layer is grown by diffusion on at least the top surface of the substrate corresponding to the at least one isolation trench. The method further includes etching the oxide layer and at least a portion of the substrate to form at least one isolation trench opening.

摘要翻译： 用于形成半导体隔离沟槽的方法包括在衬底上形成衬垫氧化物层，并在衬底上形成阻挡层。 掩模层形成在阻挡层之上，并被图案化以在掩模层中形成至少一个开口。 阻挡层的至少一部分和衬垫氧化物层的至少一部分被蚀刻穿过至少一个开口，导致沟槽衬垫氧化物层。 沟槽衬垫氧化物层的蚀刻基本上在隔离沟槽内的衬底顶表面上停止。 氧化物层通过扩散至少对应于至少一个隔离沟槽的衬底的顶表面生长。 所述方法还包括蚀刻所述氧化物层和所述衬底的至少一部分以形成至少一个隔离沟槽开口。

公开(公告)号：US20070264839A1

公开(公告)日：2007-11-15

申请号：US11433298

申请日：2006-05-12

申请人： Toni Van Gompel ,  Kuang-hsin Chen ,  Laegu Kang ,  Rode Mora ,  Michael Turner

发明人： Toni Van Gompel ,  Kuang-hsin Chen ,  Laegu Kang ,  Rode Mora ,  Michael Turner

IPC分类号： H01L21/31 ,  H01L21/469

CPC分类号： H01L21/31111 ,  H01L21/3105 ,  H01L21/31116 ,  H01L21/76205

摘要： A process of forming an electronic device can include patterning a semiconductor layer to define an opening extending to an insulating layer, wherein the insulating layer lies between a substrate and the semiconductor layer. After patterning the semiconductor layer, the opening can have a bottom, and the semiconductor layer can have a sidewall and a surface. The surface can be spaced apart from the insulating layer, and the sidewall can extend from the surface towards the insulating layer. The process can also include depositing a nitride layer within the opening, wherein depositing is performed using a PECVD technique. The process can further include densifying the nitride layer. The process can still further include removing a part of the nitride layer, wherein a remaining portion of the nitride layer can lie within the opening and be spaced apart from the surface.

摘要翻译： 形成电子器件的过程可以包括图案化半导体层以限定延伸到绝缘层的开口，其中绝缘层位于衬底和半导体层之间。 在图案化半导体层之后，开口可以具有底部，并且半导体层可以具有侧壁和表面。 表面可以与绝缘层间隔开，并且侧壁可以从表面延伸到绝缘层。 该方法还可以包括在开口内沉积氮化物层，其中使用PECVD技术进行沉积。 该方法还可以包括使氮化物层致密化。 该方法还可以进一步包括去除氮化物层的一部分，其中氮化物层的剩余部分可以位于开口内并且与表面间隔开。

公开(公告)号：US20070224772A1

公开(公告)日：2007-09-27

申请号：US11386539

申请日：2006-03-21

申请人： Mark Hall ,  Rode Mora ,  Michael Turner ,  Laegu Kang ,  Toni Van Gompel ,  Stanley Filipiak

发明人： Mark Hall ,  Rode Mora ,  Michael Turner ,  Laegu Kang ,  Toni Van Gompel ,  Stanley Filipiak

IPC分类号： H01L21/76

CPC分类号： H01L21/76283 ,  H01L21/76286 ,  H01L21/823807 ,  H01L21/823878 ,  H01L29/7846

摘要： A method for making a semiconductor device is provided herein. In accordance with the method, a semiconductor structure is provided which comprises an active semiconductor layer (224) disposed on a buried dielectric layer (222). A trench (229) is created in the semiconductor structure which exposes a portion of the buried dielectric layer. An oxide layer (250) is formed over the surfaces of the trench, and at least one stressor structure (255) is formed over the oxide layer.

摘要翻译： 本发明提供制造半导体器件的方法。 根据该方法，提供了一种半导体结构，其包括设置在掩埋介电层（222）上的有源半导体层（224）。 在半导体结构中形成沟槽（229），其暴露了一部分埋入的介质层。 在沟槽的表面上形成氧化物层（250），在氧化物层上形成至少一个应力源结构（255）。