Handlebar End Caps for Bicycle
    2.
    发明申请
    Handlebar End Caps for Bicycle 审中-公开
    自行车手柄端盖

    公开(公告)号:US20160107717A1

    公开(公告)日:2016-04-21

    申请号:US14876865

    申请日:2015-10-07

    申请人: Chih-Hsien Chen

    发明人: Chih-Hsien Chen

    IPC分类号: B62K21/12

    CPC分类号: B62K21/12

    摘要: A handlebar end cap for a bicycle contains: a body, a retaining member, and a cover. The body includes a hole, at least one end face, and a fixing groove with a second inner diameter. The hole has a first inner diameter, and the body further includes a slot. The retaining member includes a recess and a first outer diameter, the first outer diameter has a circular locking loop, and the locking loop has a second outer diameter. The retaining member further includes a positioning rib and a limiting notch, the positioning rib has a third inner diameter, and the limiting notch has a fourth inner diameter. The cover includes a covering face, and the cover includes a first locating trench and a defining portion, wherein the first locating trench has a third outer diameter, the defining portion has a fourth outer diameter.

    摘要翻译: 用于自行车的把手端盖包括:主体,保持构件和盖。 主体包括孔,至少一个端面和具有第二内径的固定槽。 孔具有第一内径,并且主体还包括槽。 保持构件包括凹部和第一外径,第一外径具有圆形锁定环,并且锁定环具有第二外径。 保持构件还包括定位肋和限位凹口,定位肋具有第三内径,并且限位凹口具有第四内径。 所述盖包括覆盖面,并且所述盖包括第一定位沟槽和限定部分,其中所述第一定位沟槽具有第三外径,所述限定部分具有第四外径。

    Bottom-Gate Thin Film Transistor and Method of Fabricating the Same
    3.
    发明申请
    Bottom-Gate Thin Film Transistor and Method of Fabricating the Same 有权
    底栅薄膜晶体管及其制造方法

    公开(公告)号:US20100096630A1

    公开(公告)日:2010-04-22

    申请号:US12400171

    申请日:2009-03-09

    IPC分类号: H01L29/786 H01L21/336

    摘要: A bottom-gate thin film transistor includes a gate electrode, a gate insulating layer and a microcrystalline silicon layer. The gate electrode is disposed on a substrate. The gate insulating layer is made up of silicon nitride and disposed on the gate electrode and the substrate. The microcrystalline silicon layer is disposed on the gate insulating layer and corresponds to the gate electrode, in which a contact interface between the gate insulating layer and the microcrystalline silicon layer has a plurality of oxygen atoms, and concentration of the oxygen atoms ranges between 1020 atoms/cm3 and 1025 atoms/cm3. A method of fabricating a bottom-gate thin film transistor is also disclosed herein.

    摘要翻译: 底栅薄膜晶体管包括栅电极,栅极绝缘层和微晶硅层。 栅电极设置在基板上。 栅极绝缘层由氮化硅构成并且设置在栅电极和基板上。 微晶硅层设置在栅极绝缘层上,对应于栅电极,其中栅极绝缘层和微晶硅层之间的接触界面具有多个氧原子,氧原子的浓度范围在1020原子之间 / cm3和1025原子/ cm3。 本文还公开了制造底栅薄膜晶体管的方法。

    Handlebar end caps for bicycle
    5.
    发明授权
    Handlebar end caps for bicycle 有权
    自行车手柄端盖

    公开(公告)号:US09469367B2

    公开(公告)日:2016-10-18

    申请号:US14876865

    申请日:2015-10-07

    申请人: Chih-Hsien Chen

    发明人: Chih-Hsien Chen

    IPC分类号: B62K21/12

    CPC分类号: B62K21/12

    摘要: A handlebar end cap for a bicycle contains: a body, a retaining member, and a cover. The body includes a hole, at least one end face, and a fixing groove with a second inner diameter. The hole has a first inner diameter, and the body further includes a slot. The retaining member includes a recess and a first outer diameter, the first outer diameter has a circular locking loop, and the locking loop has a second outer diameter. The retaining member further includes a positioning rib and a limiting notch, the positioning rib has a third inner diameter, and the limiting notch has a fourth inner diameter. The cover includes a covering face, and the cover includes a first locating trench and a defining portion. The first locating trench has a third outer diameter, and the defining portion has a fourth outer diameter.

    摘要翻译: 用于自行车的把手端盖包括:主体,保持构件和盖。 主体包括孔,至少一个端面和具有第二内径的固定槽。 孔具有第一内径,并且主体还包括槽。 保持构件包括凹部和第一外径,第一外径具有圆形锁定环,并且锁定环具有第二外径。 保持构件还包括定位肋和限位凹口,定位肋具有第三内径,并且限位凹口具有第四内径。 所述盖包括覆盖面,并且所述盖包括第一定位沟槽和限定部分。 第一定位槽具有第三外径,并且限定部具有第四外径。

    METHOD FOR MANUFACTURING THROUGH-SILICON VIA
    6.
    发明申请
    METHOD FOR MANUFACTURING THROUGH-SILICON VIA 有权
    通过硅制造方法

    公开(公告)号:US20130011938A1

    公开(公告)日:2013-01-10

    申请号:US13176790

    申请日:2011-07-06

    摘要: A method for manufacturing TSVs, wherein the method comprises several steps as follows: A stack structure having a substrate and an ILD layer (inter layer dielectric layer) is provided, in which an opening penetrating through the ILD layer and further extending into the substrate is formed. After an insulator layer and a metal barrier layer are formed on the stack structure and the sidewalls of the opening, a top metal layer is then formed on the stack structure to fulfill the opening. A first planarization process stopping on the barrier layer is conducted to remove a portion of the top metal layer. A second planarization process stopping on the ILD layer is subsequently conducted to remove a portion of the metal barrier layer, a portion of the insulator layer and a portion of the top metal layer, wherein the second planarization process has a polishing endpoint determined by a light interferometry or a motor current.

    摘要翻译: 一种制造TSV的方法,其中该方法包括以下几个步骤:提供具有基板和ILD层(层间电介质层)的堆叠结构,其中穿透ILD层并进一步延伸到基板中的开口是 形成。 在堆叠结构和开口的侧壁上形成绝缘体层和金属阻挡层之后,在堆叠结构上形成顶部金属层以实现开口。 进行停止在阻挡层上的第一平面化处理以去除顶部金属层的一部分。 随后进行停止在ILD层上的第二平坦化处理以去除金属阻挡层的一部分,绝缘体层的一部分和顶部金属层的一部分,其中第二平坦化工艺具有由光线确定的抛光终点 干涉测量或电机电流。

    Bottom-gate thin film transistor and method of fabricating the same
    7.
    发明授权
    Bottom-gate thin film transistor and method of fabricating the same 有权
    底栅薄膜晶体管及其制造方法

    公开(公告)号:US08084771B2

    公开(公告)日:2011-12-27

    申请号:US12893063

    申请日:2010-09-29

    摘要: A bottom-gate thin film transistor includes a gate electrode, a gate insulating layer and a microcrystalline silicon layer. The gate electrode is disposed on a substrate. The gate insulating layer is made up of silicon nitride and disposed on the gate electrode and the substrate. The microcrystalline silicon layer is disposed on the gate insulating layer and corresponds to the gate electrode, in which a contact interface between the gate insulating layer and the microcrystalline silicon layer has a plurality of oxygen atoms, and concentration of the oxygen atoms ranges between 1020 atoms/cm3 and 1025 atoms/cm3. A method of fabricating a bottom-gate thin film transistor is also disclosed herein.

    摘要翻译: 底栅薄膜晶体管包括栅电极,栅极绝缘层和微晶硅层。 栅电极设置在基板上。 栅极绝缘层由氮化硅构成并且设置在栅电极和基板上。 微晶硅层设置在栅极绝缘层上,对应于栅电极,其中栅极绝缘层和微晶硅层之间的接触界面具有多个氧原子,氧原子的浓度范围在1020原子之间 / cm3和1025原子/ cm3。 本文还公开了制造底栅薄膜晶体管的方法。

    Method for wafer-level package
    8.
    发明授权
    Method for wafer-level package 有权
    晶圆级封装方法

    公开(公告)号:US07361284B2

    公开(公告)日:2008-04-22

    申请号:US11426013

    申请日:2006-06-23

    申请人: Chih-Hsien Chen

    发明人: Chih-Hsien Chen

    IPC分类号: H01B13/00

    摘要: A method for wafer-level package. A cap wafer having cavities is bonded to a support wafer, and a portion of the cap wafer is etched through. The cap wafer is released from the support wafer, and bonded to a transparent wafer, and a portion of the cap wafer corresponding to the cavities is removed so that the remaining cap wafer forms a plurality of support blocks. A device wafer is provided, and the support blocks are bonded to the device wafer so that the support blocks and the transparent wafer hermitically seal the devices disposed in the device wafer.

    摘要翻译: 晶圆级封装的方法。 将具有空穴的盖片结合到支撑晶片上,并且盖晶片的一部分被蚀刻通过。 盖晶片从支撑晶片释放并结合到透明晶片,并且去除与空腔相对应的盖晶片的一部分,使得剩余的盖晶片形成多个支撑块。 提供了器件晶片,并且支撑块被结合到器件晶片,使得支撑块和透明晶片密封地密封设置在器件晶片中的器件。

    METHOD FOR WAFER-LEVEL PACKAGE
    9.
    发明申请
    METHOD FOR WAFER-LEVEL PACKAGE 有权
    用于水平包装的方法

    公开(公告)号:US20070218584A1

    公开(公告)日:2007-09-20

    申请号:US11426013

    申请日:2006-06-23

    申请人: Chih-Hsien Chen

    发明人: Chih-Hsien Chen

    IPC分类号: H01L21/00

    摘要: A method for wafer-level package. A cap wafer having cavities is bonded to a support wafer, and a portion of the cap wafer is etched through. The cap wafer is released from the support wafer, and bonded to a transparent wafer, and a portion of the cap wafer corresponding to the cavities is removed so that the remaining cap wafer forms a plurality of support blocks. A device wafer is provided, and the support blocks are bonded to the device wafer so that the support blocks and the transparent wafer hermitically seal the devices disposed in the device wafer.

    摘要翻译: 晶圆级封装的方法。 将具有空穴的盖片结合到支撑晶片上,并且盖晶片的一部分被蚀刻通过。 盖晶片从支撑晶片释放并结合到透明晶片,并且去除与空腔相对应的盖晶片的一部分,使得剩余的盖晶片形成多个支撑块。 提供了器件晶片,并且支撑块被结合到器件晶片,使得支撑块和透明晶片密封地密封设置在器件晶片中的器件。

    METHOD FOR WAFER LEVEL PACKAGING
    10.
    发明申请
    METHOD FOR WAFER LEVEL PACKAGING 审中-公开
    用于水平包装的方法

    公开(公告)号:US20060160273A1

    公开(公告)日:2006-07-20

    申请号:US10906935

    申请日:2005-03-14

    申请人: Chih-Hsien Chen

    发明人: Chih-Hsien Chen

    IPC分类号: H01L21/46

    摘要: A device wafer including a plurality of devices and a plurality of contact pads positioned on a top surface of the device wafer and electrically connected to the devices is provided. Subsequently, a cap wafer is provided. Following that, a plurality of bonding patterns and a plurality of cavity patterns are formed on a bottom surface of the cap wafer. Thereafter, the top surface of the device wafer and the bottom surface of the cap wafer are bonded together with the bonding patterns, wherein the cavity patterns are aligned to the contact pads.

    摘要翻译: 提供了包括多个器件的器件晶片和设置在器件晶片的顶表面上并电连接到器件的多个接触焊盘。 随后,提供盖晶片。 接着,在盖晶片的底面上形成多个接合图形和多个空腔图案。 此后,器件晶片的顶表面和盖晶片的底表面与接合图案结合在一起,其中腔图案与接触垫对准。