-
公开(公告)号:US07515504B2
公开(公告)日:2009-04-07
申请号:US11969404
申请日:2008-01-04
IPC分类号: G11C8/00
CPC分类号: G11C7/04 , G06F13/4243 , G11C7/1066 , G11C7/22 , G11C7/222 , G11C11/401 , G11C11/4076 , G11C11/4093 , G11C29/02 , G11C29/022 , G11C29/023 , G11C29/028 , H03K2005/00052 , H03L7/0805 , H03L7/0812 , H03L7/183 , H03L7/23
摘要: A system and method are used to allow high speed communication between a circuit and an external device. The system and method include a PLL with multiple phased outputs configured to be controlled digitally, a deskew PLL configured to align a clock of controller circuitry to interface circuitry, and a phase interpolated voltage controlled delay line configured to phase shift incoming signals. Analog design techniques of phase interpolation accurately position clocks and strobe signals that are required for high speed interfaces. The high speed interface is for transmitting and receiving signals from the external device, for example, a DDR DRAM.
摘要翻译: 一种系统和方法用于允许电路和外部设备之间的高速通信。 该系统和方法包括配置为被数字控制的多个相控输出的PLL,被配置为将控制器电路的时钟与接口电路对准的偏移校准PLL以及被配置为相移输入信号的相位内插电压控制延迟线。 相位插值的模拟设计技术可精确定位高速接口所需的时钟和选通信号。 高速接口用于从外部设备发送和接收信号,例如DDR DRAM。
-
公开(公告)号:US07333390B2
公开(公告)日:2008-02-19
申请号:US11287380
申请日:2005-11-28
IPC分类号: G11C8/00
CPC分类号: G11C7/04 , G06F13/4243 , G11C7/1066 , G11C7/22 , G11C7/222 , G11C11/401 , G11C11/4076 , G11C11/4093 , G11C29/02 , G11C29/022 , G11C29/023 , G11C29/028 , H03K2005/00052 , H03L7/0805 , H03L7/0812 , H03L7/183 , H03L7/23
摘要: A system and method are used to allow high speed communication between a chip and an external device. The system and method include a PLL with multiple phased outputs configured to be controlled digitally, a deskew PLL configured to align a clock of controller circuitry to interface circuitry, and a phase interpolated voltage controlled delay line configured to phase shift incoming signals. Analog design techniques of phase interpolation accurately position clocks and strobe signals that are required for high speed interfaces. The high speed interface is for transmitting and receiving signals from the external device, for example, a DDR DRAM.
摘要翻译: 使用系统和方法来允许芯片和外部设备之间的高速通信。 该系统和方法包括配置为被数字控制的多个相控输出的PLL,被配置为将控制器电路的时钟与接口电路对准的偏移校准PLL以及被配置为相移输入信号的相位内插电压控制延迟线。 相位插值的模拟设计技术可精确定位高速接口所需的时钟和选通信号。 高速接口用于从外部设备发送和接收信号,例如DDR DRAM。
-
公开(公告)号:US06975557B2
公开(公告)日:2005-12-13
申请号:US10832262
申请日:2004-04-27
IPC分类号: G06F13/42 , G11C7/22 , G11C11/4076 , G11C11/4093 , G11C8/00
CPC分类号: G11C7/04 , G06F13/4243 , G11C7/1066 , G11C7/22 , G11C7/222 , G11C11/401 , G11C11/4076 , G11C11/4093 , G11C29/02 , G11C29/022 , G11C29/023 , G11C29/028 , H03K2005/00052 , H03L7/0805 , H03L7/0812 , H03L7/183 , H03L7/23
摘要: A system and method are used to allow high speed communication between a chip and an external device. The system and method include a PLL with multiple phased outputs configured to be controlled digitally, a deskew PLL configured to align a clock of controller circuitry to interface circuitry, and a phase interpolated voltage controlled delay line configured to phase shift incoming signals. Analog design techniques of phase interpolation accurately position clocks and strobe signals that are required for high speed interfaces. The high speed interface is for transmitting and receiving signals from the external device, for example, a DDR DRAM.
摘要翻译: 使用系统和方法来允许芯片和外部设备之间的高速通信。 该系统和方法包括配置为被数字控制的多个相控输出的PLL,被配置为将控制器电路的时钟与接口电路对准的偏移校准PLL以及被配置为相移输入信号的相位内插电压控制延迟线。 相位插值的模拟设计技术可精确定位高速接口所需的时钟和选通信号。 高速接口用于从外部设备发送和接收信号,例如DDR DRAM。
-
-