公开(公告)号：US06622907B2

公开(公告)日：2003-09-23

申请号：US10078948

申请日：2002-02-19

申请人： Lisa A. Fanti ,  Randolph F. Knarr ,  Erik J. Roggeman ,  Kamalesh K. Srivastava

发明人： Lisa A. Fanti ,  Randolph F. Knarr ,  Erik J. Roggeman ,  Kamalesh K. Srivastava

IPC分类号： B23K3102

CPC分类号： H01L24/05 ,  B23K35/001 ,  B23K35/007 ,  H01L21/2885 ,  H01L24/03 ,  H01L24/11 ,  H01L2224/03912 ,  H01L2224/03914 ,  H01L2224/0401 ,  H01L2224/05599 ,  H01L2224/11472 ,  H01L2224/13023 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01059 ,  H01L2924/01074 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/00014

摘要： Start with a semiconductor substrate with contacts exposed through an insulating layer. Form a base over the contacts, with the base composed of at least one metal layer. Then form a conductive metal layer over the base. Form a mask over the top surface of the conductive metal layer with C4 solder bump openings therethrough with the shape of C4 solder bump images down to the surface of the conductive metal layer above the contacts. Etch away the exposed portions of the conductive metal layer below the C4 solder bump openings to form through holes in the conductive metal layer exposing C4 solder bump plating sites on the top surface of the base below the C4 solder bump openings with the conductive metal layer remaining intact on the periphery of the through holes at the C4 solder bump plating sites. As an option, form a barrier layer over the plating sites next. Form C4 solder bumps on the plating sites on the base/barrier layer within the C4 solder bump openings, with the C4 solder bumps being in contact with the conductive metal layer on the periphery of the through holes. Remove the mask. Etch away the remainder of the conductive metal layer, and etch away the base aside from the C4 solder bumps forming BLM pads. Then reflow the C4 solder bumps to form C4 solder balls.

摘要翻译： 从具有通过绝缘层暴露的触点的半导体衬底开始。 在触点上形成一个基底，底部由至少一个金属层组成。 然后在基底上形成导电金属层。 在导电金属层的顶表面上形成具有C4焊料凸块开口的掩模，其中C4焊料凸块图像的形状向下到触点上方的导电金属层的表面。 将C4导电金属层下方的导电金属层的露出部分刻蚀掉，以形成导电金属层中的通孔，露出C4焊料凸块开口下方的基座顶面上的C4焊料凸块电镀部位，导电金属层保留 在C4焊料凸点电镀部位的通孔的外围是完整的。 作为选择，接下来在电镀位置上形成阻挡层。 在C4焊料凸点开口内的基底/阻挡层上的电镀部位上形成C4焊料凸块，其中C4焊料凸块与通孔周边上的导电金属层接触。 取下面具。 蚀刻掉导电金属层的剩余部分，并且除了形成BLM焊盘的C4焊料凸块之外蚀刻掉基部。 然后回流C4焊锡凸块形成C4焊球。

公开(公告)号：US07572726B2

公开(公告)日：2009-08-11

申请号：US11271760

申请日：2005-11-10

申请人： Julie C. Biggs ,  Tien-Jen Cheng ,  David E. Eichstadt ,  Lisa A. Fanti ,  Jonathan H. Griffith ,  Randolph F. Knarr ,  Sarah H. Knickerbocker ,  Kevin S. Petrarca ,  Roger A. Quon ,  Wolfgang Sauter ,  Kamalesh K. Srivastava ,  Richard P. Volant

发明人： Julie C. Biggs ,  Tien-Jen Cheng ,  David E. Eichstadt ,  Lisa A. Fanti ,  Jonathan H. Griffith ,  Randolph F. Knarr ,  Sarah H. Knickerbocker ,  Kevin S. Petrarca ,  Roger A. Quon ,  Wolfgang Sauter ,  Kamalesh K. Srivastava ,  Richard P. Volant

IPC分类号： H01L21/44

CPC分类号： H01L24/05 ,  H01L24/03 ,  H01L24/45 ,  H01L24/48 ,  H01L24/85 ,  H01L2224/04042 ,  H01L2224/05083 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05181 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/45144 ,  H01L2224/48453 ,  H01L2224/48463 ,  H01L2224/4847 ,  H01L2224/48624 ,  H01L2224/48644 ,  H01L2224/48655 ,  H01L2224/85205 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01073 ,  H01L2924/01076 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01327 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00015

摘要： A method of forming wire bonds in (I/C) chips comprising: providing an I/C chip having a conductive pad for a wire bond with at least one layer of dielectric material overlying the pad; forming an opening through the dielectric material exposing a portion of said pad. Forming at least a first conductive layer on the exposed surface of the pad and on the surface of the opening. Forming a seed layer on the first conductive layer; applying a photoresist over the seed layer; exposing and developing the photoresist revealing the surface of the seed layer surrounding the opening; removing the exposed seed layer; removing the photoresist material in the opening revealing the seed layer. Plating at least one second layer of conductive material on the seed layer in the opening, and removing the first conductive layer on the dielectric layer around the opening. The invention also includes the resulting structure.

摘要翻译： 一种在（I / C）芯片中形成引线键合的方法，包括：提供具有导电焊盘的I / C芯片，所述导电焊盘与覆盖所述焊盘的至少一层电介质材料进行引线接合; 通过暴露所述垫的一部分的电介质材料形成开口。 在衬垫的暴露表面和开口表面上形成至少第一导电层。 在第一导电层上形成种子层; 在种子层上施加光致抗蚀剂; 曝光和显影光致抗蚀剂，其显露出围绕开口的种子层的表面; 去除暴露的种子层; 去除开口中的光致抗蚀剂材料，露出种子层。 在开口中的种子层上电镀至少一层第二导电材料层，以及去除围绕开口的电介质层上的第一导电层。 本发明还包括所得到的结构。

公开(公告)号：US06995475B2

公开(公告)日：2006-02-07

申请号：US10666775

申请日：2003-09-18

申请人： Julie C. Biggs ,  Tien-Jen Cheng ,  David E. Eichstadt ,  Lisa A. Fanti ,  Jonathan H. Griffith ,  Randolph F. Knarr ,  Sarah H. Knickerbocker ,  Kevin S. Petrarca ,  Roger A. Quon ,  Wolfgang Sauter ,  Kamalesh K. Srivastava ,  Richard P. Volant

发明人： Julie C. Biggs ,  Tien-Jen Cheng ,  David E. Eichstadt ,  Lisa A. Fanti ,  Jonathan H. Griffith ,  Randolph F. Knarr ,  Sarah H. Knickerbocker ,  Kevin S. Petrarca ,  Roger A. Quon ,  Wolfgang Sauter ,  Kamalesh K. Srivastava ,  Richard P. Volant

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L24/05 ,  H01L24/03 ,  H01L24/45 ,  H01L24/48 ,  H01L24/85 ,  H01L2224/04042 ,  H01L2224/05083 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05181 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/45144 ,  H01L2224/48453 ,  H01L2224/48463 ,  H01L2224/4847 ,  H01L2224/48624 ,  H01L2224/48644 ,  H01L2224/48655 ,  H01L2224/85205 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01073 ,  H01L2924/01076 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01327 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00015

摘要： A method of forming wire bonds in (I/C) chips comprising: providing an I/C chip having a conductive pad for a wire bond with at least one layer of dielectric material overlying the pad; forming an opening through the dielectric material exposing a portion of said pad. Forming at least a first conductive layer on the exposed surface of the pad and on the surface of the opening. Forming a seed layer on the first conductive layer; applying a photoresist over the seed layer; exposing and developing the photoresist revealing the surface of the seed layer surrounding the opening; removing the exposed seed layer; removing the photoresist material in the opening revealing the seed layer. Plating at least one second layer of conductive material on the seed layer in the opening, and removing the first conductive layer on the dielectric layer around the opening. The invention also includes the resulting structure.

摘要翻译： 一种在（I / C）芯片中形成引线键合的方法，包括：提供具有导电焊盘的I / C芯片，所述导电焊盘与覆盖所述焊盘的至少一层电介质材料进行引线接合; 通过暴露所述垫的一部分的电介质材料形成开口。 在衬垫的暴露表面和开口表面上形成至少第一导电层。 在第一导电层上形成种子层; 在种子层上施加光致抗蚀剂; 曝光和显影光致抗蚀剂，其显露出围绕开口的种子层的表面; 去除暴露的种子层; 去除开口中的光致抗蚀剂材料，露出种子层。 在开口中的种子层上电镀至少一层第二导电材料层，以及去除围绕开口的电介质层上的第一导电层。 本发明还包括所得到的结构。

公开(公告)号：US06661100B1

公开(公告)日：2003-12-09

申请号：US10210631

申请日：2002-07-30

申请人： Brent A. Anderson ,  Randolph F. Knarr ,  Sarah H. Knickerbocker ,  Edmund J. Sprogis ,  Kamalesh K. Srivastava

发明人： Brent A. Anderson ,  Randolph F. Knarr ,  Sarah H. Knickerbocker ,  Edmund J. Sprogis ,  Kamalesh K. Srivastava

IPC分类号： H01L2348

CPC分类号： H01L23/49816 ,  H01L23/13 ,  H01L23/5286 ,  H01L25/0657 ,  H01L2224/16 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06555 ,  H01L2225/06586 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/3011

摘要： A low impedance power distribution structure and method for substrate packaging of semiconductor chips containing very large scale integrated circuit (VLSI) circuits, such as microprocessors and associated memory, is presented. The power distribution structure incorporates under bump metallurgy (UBM) solder bump forming technology to produce not only solder bump connections that are vertically oriented, but also low impedance distribution wires that are horizontally oriented, and which provide electrical interconnection between various selected electrical contact points, such as solder bumps. These low impedance distribution wires introduce the benefits of low characteristic impedance to the substrate's power distribution structure.

摘要翻译： 提出了一种用于包含诸如微处理器和相关存储器之类的大规模集成电路（VLSI）电路的半导体芯片的基板封装的低阻抗配电结构和方法。 功率分配结构包括凸块式冶金（UBM）焊料凸块形成技术，不仅产生垂直取向的焊料凸块连接，而且还产生水平定向的低阻抗分布导线，并且在各种选择的电接触点之间提供电互连， 如焊锡凸块。 这些低阻抗分布导线将低特性阻抗的优点引入衬底的配电结构。

公开(公告)号：US09111816B2

公开(公告)日：2015-08-18

申请号：US13431609

申请日：2012-03-27

申请人： Virendra R. Jadhav ,  Krystyna W. Semkow ,  Kamalesh K. Srivastava ,  Brian R. Sundlof

发明人： Virendra R. Jadhav ,  Krystyna W. Semkow ,  Kamalesh K. Srivastava ,  Brian R. Sundlof

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/00

CPC分类号： H01L24/13 ,  H01L23/562 ,  H01L24/11 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/05666 ,  H01L2224/1145 ,  H01L2224/11452 ,  H01L2224/11462 ,  H01L2224/11901 ,  H01L2224/13005 ,  H01L2224/13013 ,  H01L2224/13023 ,  H01L2224/1308 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13166 ,  H01L2224/13171 ,  H01L2224/13184 ,  H01L2224/13655 ,  H01L2224/13666 ,  H01L2224/13671 ,  H01L2224/13684 ,  H01L2224/16235 ,  H01L2224/81815 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/2064 ,  H01L2924/351 ,  H01L2924/35121 ,  H01L2924/37001 ,  H01L2924/384 ,  Y10T156/10 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599

摘要： A multi-layer pillar is provided. The multi-layer pillar is used as an interconnect between a chip and substrate. The pillar has at least one low strength, high ductility deformation region configured to absorb force imposed during chip assembly and thermal excursions.

摘要翻译： 提供多层支柱。 多层柱用作芯片和基板之间的互连。 支柱具有至少一个低强度，高延展性变形区域，其被配置为吸收在芯片组装和热偏移期间施加的力。

公开(公告)号：US07952207B2

公开(公告)日：2011-05-31

申请号：US11950431

申请日：2007-12-05

申请人： Virendra R. Jadhav ,  Jayshree Shah ,  Kamalesh K. Srivastava

发明人： Virendra R. Jadhav ,  Jayshree Shah ,  Kamalesh K. Srivastava

IPC分类号： H01L23/52

CPC分类号： H01L23/49816 ,  H01L24/10 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/0558 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13118 ,  H01L2224/1312 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01051 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/14 ,  H05K3/3436 ,  H05K3/3452 ,  H05K3/4007 ,  H05K2201/0367 ,  H05K2201/09436 ,  Y02P70/613 ,  H01L2924/00014 ,  H01L2924/00

摘要： Disclosed are embodiments of a flip-chip assembly and method using lead-free solder. This assembly incorporates mushroom-plated metal layers that fill and overflow solder resist openings on an organic laminate substrate. The lower portion of metal layer provides structural support to its corresponding solder resist opening. The upper portion (i.e., cap) of each metal layer provides a landing spot for a solder joint between an integrated circuit device and the substrate and, thereby, allows for enhanced solder volume control. The additional structural support, in combination with the enhanced solder volume control, minimizes strain on the resulting solder joints. Additionally, the cap further allows the minimum diameter of the solder joint on the substrate-side of the assembly to be larger than the diameter of the solder resist opening. Thus, the invention decouples C4 reliability concerns from laminate design concerns and, thereby, allows for greater design flexibility.

摘要翻译： 公开了使用无铅焊料的倒装芯片组装和方法的实施例。 该组件包括在有机层压基板上填充和溢出阻焊剂开口的蘑菇镀金属层。 金属层的下部为其相应的抗焊剂开口提供结构支撑。 每个金属层的上部（即盖）为集成电路器件和衬底之间的焊接点提供着陆点，从而允许增强的焊料体积控制。 额外的结构支撑与增强的焊料体积控制相结合，最大限度地减少了所得到的焊点的应变。 此外，帽还允许组件的衬底侧上的焊点的最小直径大于阻焊剂开口的直径。 因此，本发明将C4可靠性问题与层压板设计问题分开，从而允许更大的设计灵活性。

公开(公告)号：US07425278B2

公开(公告)日：2008-09-16

申请号：US11563858

申请日：2006-11-28

申请人： Krystyna Waleria Semkow ,  Anurag Jain ,  Kamalesh K. Srivastava

发明人： Krystyna Waleria Semkow ,  Anurag Jain ,  Kamalesh K. Srivastava

IPC分类号： C23C1/00

CPC分类号： H01L21/32134

摘要： An etchant which includes an aqueous solution of between about 30% and about 38% concentrated hydrogen peroxide, said percentages being by volume, based on the total volume of the solution; between about 3.5 ml and about 20 ml per liter of phosphoric acid; and an amount of potassium hydroxide to adjust the pH of the solution to between about 7.8 and about 9.1. The etchant is useful in removing a layer of an alloy of titanium and tungsten or a layer of tungsten from a precision surface.

摘要翻译： 包括约30％至约38％浓缩的过氧化氢的水溶液的蚀刻剂，所述百分比基于溶液的总体积计; 约3.5ml至约20ml /升磷酸; 和一定量的氢氧化钾以将溶液的pH调节至约7.8至约9.1。 蚀刻剂可用于从精密表面去除钛和钨的合金层或钨层。

公开(公告)号：US06293457B1

公开(公告)日：2001-09-25

申请号：US09590119

申请日：2000-06-08

申请人： Kamalesh K. Srivastava ,  Jonathan H. Griffith ,  Mary C. Cullinan-Scholl ,  William H. Brearley ,  Peter C. Wade

发明人： Kamalesh K. Srivastava ,  Jonathan H. Griffith ,  Mary C. Cullinan-Scholl ,  William H. Brearley ,  Peter C. Wade

IPC分类号： B23K3102

CPC分类号： H01L24/05 ,  C23F1/26 ,  H01L21/76804 ,  H01L24/03 ,  H01L24/11 ,  H01L24/81 ,  H01L2224/0347 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05082 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/1147 ,  H01L2224/11912 ,  H01L2224/13023 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/81801 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01016 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0105 ,  H01L2924/01059 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/3011 ,  H01L2924/00014

摘要： Form a solder connector on a semiconductor device starting with a first step of forming at least one dielectric layer over a doped semiconductor substrate. Then form a hole through the dielectric layer down to the semiconductor substrate. Form a metal conductor in the hole. Form intermediate layers over the metal conductor and the dielectric layer. Then form a tapered opening down to the surface of the metal conductor. Form BLM layers including a titanium-tungsten (TiW) layer over the metal conductor and the dielectric layer with the remainder of the BLM layers being formed over the TiW layer. Form a mask over the top surface of the BLM layers with a patterning through hole located above the metal conductor exposing a portion of the surface of the BLM layers. Plate a C4 solder bump on the BLM layers in the patterning hole. Remove the mask. Wet etch away the BLM layers aside from the solder bump leaving a residual TiW layer over the dielectric layer. Perform a dry etching process to remove the residual TiW layer aside from the solder bump. Then, end the dry etching when the end point has been reached. Finally, heat the solder bump in a reflow process to form a C4 solder ball.

摘要翻译： 在半导体器件上形成焊料连接器，从在掺杂半导体衬底上形成至少一个电介质层的第一步骤开始。 然后通过介电层形成一个穿过半导体衬底的孔。 在孔中形成金属导体。 在金属导体和电介质层上形成中间层。 然后形成锥形开口，直到金属导体的表面。 在金属导体上形成包括钛 - 钨（TiW）层的BLM层，其中剩余的BLM层形成在TiW层上。 在BLM层的顶表面上形成掩模，其中图案化通孔位于金属导体上方，露出BLM层表面的一部分。 在图案化孔中的BLM层上贴上C4焊料凸块。 取下面具。 湿式蚀刻除了焊料凸块之外的BLM层，在电介质层上留下残留的TiW层。 执行干蚀刻工艺以除去焊料凸块之外的残余TiW层。 然后，当达到终点时结束干蚀刻。 最后，在回流焊过程中加热焊料凸块以形成C4焊球。

公开(公告)号：US07784669B2

公开(公告)日：2010-08-31

申请号：US12536122

申请日：2009-08-05

申请人： Gareth G. Hougham ,  Kamalesh K. Srivastava ,  Sung K. Kang ,  Da-Yuan Shih ,  Brian R. Sundlof ,  S. Jay Chey ,  Donald W. Henderson ,  David R. Di Milia ,  Richard P. Ferlita ,  Roy A. Carruthers

发明人： Gareth G. Hougham ,  Kamalesh K. Srivastava ,  Sung K. Kang ,  Da-Yuan Shih ,  Brian R. Sundlof ,  S. Jay Chey ,  Donald W. Henderson ,  David R. Di Milia ,  Richard P. Ferlita ,  Roy A. Carruthers

IPC分类号： B23K35/24

CPC分类号： B23K1/19 ,  B23K35/262 ,  H05K3/3436 ,  H05K3/3463 ,  H05K2201/0215

摘要： Briefly, a novel material process is disclosed wherein one or more nucleation modifiers are added, in trace amounts, to a lead-free tin-rich solder alloy to produce a solder composition with reduce or suppressed undercooling temperature characteristics. The modifier being a substance which facilitates the reduction of extreme anisotropic properties associated with body-centered-tetragonal tin based lead-free solder. The addition of the nucleation modifiers to the solder alloy does not materially effect the solder composition's melting point. As such, balls of solder with the nucleated composition freeze while other solder balls within the array remain in the melt. This effectively enables one substrate to be pinned to another substrate by one or more predetermined solder balls to secure the package while the remaining solder joints are in the liquid state. Further, the addition of a trace amount of nucleation sites within the composition facilitates control over the number, size, and orientations of primary intermetallic compounds in tin rich crystallite grains. Moreover, trace amounts of one or more solid and/or insoluble nucleating modifiers within a given volume of solder reduces the size of average crystallites within the composition.

摘要翻译： 简而言之，公开了一种新颖的材料方法，其中将一种或多种成核改性剂以微量添加到无铅富锡焊料合金中以产生具有降低或抑制的过冷温度特性的焊料组合物。 该改性剂是有助于减少与体心四方锡锡基无铅焊料相关的极端各向异性的物质。 将成核改性剂添加到焊料合金中不会实质上影响焊料组合物的熔点。 因此，具有成核组合物的焊料球冻结，而阵列内的其它焊球保持在熔体中。 这有效地使一个基板通过一个或多个预定的焊球被固定到另一个基板，以固定封装，而剩余的焊点处于液态。 此外，在组合物中添加微量的成核位点有助于控制富锡微晶颗粒中初级金属间化合物的数量，尺寸和取向。 此外，在给定体积的焊料中痕量的一种或多种固态和/或不溶性成核改性剂减少了组合物内平均微晶的尺寸。

公开(公告)号：US20100200271A1

公开(公告)日：2010-08-12

申请号：US12704592

申请日：2010-02-12

申请人： Charles L. Arvin ,  Alexandre Blander ,  Peter J. Brofman ,  Donald W. Henderson ,  Gareth G. Hougham ,  Hsichang Liu ,  Eric D. Perfecto ,  Srinivasa S.N. Reddy ,  Krystyna W. Semkow ,  Kamalesh K. Srivastava ,  Brian R. Sundlof ,  Julien Sylvestre ,  Renee L. Weisman

发明人： Charles L. Arvin ,  Alexandre Blander ,  Peter J. Brofman ,  Donald W. Henderson ,  Gareth G. Hougham ,  Hsichang Liu ,  Eric D. Perfecto ,  Srinivasa S.N. Reddy ,  Krystyna W. Semkow ,  Kamalesh K. Srivastava ,  Brian R. Sundlof ,  Julien Sylvestre ,  Renee L. Weisman

IPC分类号： H01B5/00 ,  H01R43/00

CPC分类号： H01B1/02 ,  B23K35/0244 ,  B23K35/262 ,  B23K35/36 ,  B23K35/3602 ,  B82Y30/00 ,  C22C13/00 ,  H01B13/00 ,  H01L23/49866 ,  H01L2924/0002 ,  H05K3/3436 ,  H05K3/3463 ,  H05K2201/0209 ,  H05K2201/0257 ,  Y10T29/49117 ,  H01L2924/00

摘要： In one embodiment of the present invention, inert nano-sized particles having dimensions from 1 nm to 1,000 nm are added into a solder ball. The inert nano-sized particles may comprise metal oxides, metal nitrides, metal carbides, metal borides, etc. The inert nano-sized particles may be a single compound, or may be a metallic material having a coating of a different material. In another embodiment of the present invention, a small quantity of at least one elemental metal that forms stable high melting intermetallic compound with tin is added to a solder ball. The added at least one elemental metal forms precipitates of intermetallic compounds with tin, which are dispersed as fine particles in the solder.

摘要翻译： 在本发明的一个实施方案中，将尺寸为1nm至1000nm的惰性纳米尺寸颗粒加入到焊球中。 惰性纳米尺寸颗粒可以包括金属氧化物，金属氮化物，金属碳化物，金属硼化物等。惰性纳米尺寸颗粒可以是单一化合物，或者可以是具有不同材料的涂层的金属材料。 在本发明的另一个实施方案中，将少量与锡形成稳定的高熔点金属间化合物的元素金属添加到焊料球中。 添加的至少一种元素金属与锡形成金属间化合物的沉淀物，其作为细颗粒分散在焊料中。